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File gcc-btver2.diff of Package gcc47-sp3
btver2 basic support (svn 189838 and 190151) Index: gcc/config.gcc =================================================================== --- gcc/config.gcc.orig 2013-01-03 09:59:31.000000000 +0100 +++ gcc/config.gcc 2013-01-17 17:32:41.000000000 +0100 @@ -1273,7 +1273,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfree TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'` need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1282,7 +1282,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfree ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1388,7 +1388,7 @@ i[34567]86-*-solaris2* | x86_64-*-solari tmake_file="$tmake_file i386/t-sol2-64" need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1397,7 +1397,7 @@ i[34567]86-*-solaris2* | x86_64-*-solari ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1454,7 +1454,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) if test x$enable_targets = xall; then tm_defines="${tm_defines} TARGET_BI_ARCH=1" case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1463,7 +1463,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -2734,6 +2734,10 @@ case ${target} in arch=btver1 cpu=btver1 ;; + btver2-*) + arch=btver2 + cpu=btver2 + ;; amdfam10-*|barcelona-*) arch=amdfam10 cpu=amdfam10 @@ -2831,6 +2835,10 @@ case ${target} in arch=btver1 cpu=btver1 ;; + btver2-*) + arch=btver2 + cpu=btver2 + ;; amdfam10-*|barcelona-*) arch=amdfam10 cpu=amdfam10 @@ -3266,7 +3274,7 @@ case "${target}" in ;; "" | x86-64 | generic | native \ | k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \ - | opteron-sse3 | athlon-fx | bdver2 | bdver1 | btver1 \ + | opteron-sse3 | athlon-fx | bdver2 | bdver1 | btver2 | btver1 \ | amdfam10 | barcelona | nocona | core2 | corei7 \ | corei7-avx | core-avx-i | core-avx2 | atom) # OK Index: gcc/config/i386/i386.h =================================================================== --- gcc/config/i386/i386.h.orig 2012-11-26 13:06:23.000000000 +0100 +++ gcc/config/i386/i386.h 2013-01-17 17:32:41.000000000 +0100 @@ -247,6 +247,7 @@ extern const struct processor_costs ix86 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) +#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) /* Feature tests against the various tunings. */ @@ -605,6 +606,7 @@ enum target_cpu_default TARGET_CPU_DEFAULT_bdver1, TARGET_CPU_DEFAULT_bdver2, TARGET_CPU_DEFAULT_btver1, + TARGET_CPU_DEFAULT_btver2, TARGET_CPU_DEFAULT_max }; @@ -2063,6 +2065,7 @@ enum processor_type PROCESSOR_BDVER1, PROCESSOR_BDVER2, PROCESSOR_BTVER1, + PROCESSOR_BTVER2, PROCESSOR_ATOM, PROCESSOR_max }; Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md.orig 2012-11-26 13:06:23.000000000 +0100 +++ gcc/config/i386/i386.md 2013-01-17 17:32:41.000000000 +0100 @@ -300,7 +300,7 @@ ;; Processor type. (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7, - atom,generic64,amdfam10,bdver1,bdver2,btver1" + atom,generic64,amdfam10,bdver1,bdver2,btver1,btver2" (const (symbol_ref "ix86_schedule"))) ;; A basic instruction type. Refinements due to arguments to be Index: gcc/config/i386/i386-c.c =================================================================== --- gcc/config/i386/i386-c.c.orig 2013-01-07 16:39:59.000000000 +0100 +++ gcc/config/i386/i386-c.c 2013-01-17 17:32:41.000000000 +0100 @@ -118,6 +118,10 @@ ix86_target_macros_internal (HOST_WIDE_I def_or_undef (parse_in, "__btver1"); def_or_undef (parse_in, "__btver1__"); break; + case PROCESSOR_BTVER2: + def_or_undef (parse_in, "__btver2"); + def_or_undef (parse_in, "__btver2__"); + break; case PROCESSOR_PENTIUM4: def_or_undef (parse_in, "__pentium4"); def_or_undef (parse_in, "__pentium4__"); @@ -208,6 +212,9 @@ ix86_target_macros_internal (HOST_WIDE_I case PROCESSOR_BTVER1: def_or_undef (parse_in, "__tune_btver1__"); break; + case PROCESSOR_BTVER2: + def_or_undef (parse_in, "__tune_btver2__"); + break; case PROCESSOR_PENTIUM4: def_or_undef (parse_in, "__tune_pentium4__"); break; Index: gcc/config/i386/driver-i386.c =================================================================== --- gcc/config/i386/driver-i386.c.orig 2012-10-08 14:02:55.000000000 +0200 +++ gcc/config/i386/driver-i386.c 2013-01-17 17:32:41.000000000 +0100 @@ -532,6 +532,8 @@ const char *host_detect_local_cpu (int a if (name == SIG_GEODE) processor = PROCESSOR_GEODE; + else if (has_movbe) + processor = PROCESSOR_BTVER2; else if (has_bmi) processor = PROCESSOR_BDVER2; else if (has_xop) @@ -705,6 +707,9 @@ const char *host_detect_local_cpu (int a case PROCESSOR_BTVER1: cpu = "btver1"; break; + case PROCESSOR_BTVER2: + cpu = "btver2"; + break; default: /* Use something reasonable. */ Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c.orig 2013-01-07 16:39:59.000000000 +0100 +++ gcc/config/i386/i386.c 2013-01-17 17:38:48.000000000 +0100 @@ -1508,6 +1508,85 @@ struct processor_costs btver1_cost = { 1, /* cond_not_taken_branch_cost. */ }; +struct processor_costs btver2_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (2), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (4), /* DI */ + COSTS_N_INSNS (5)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (35), /* HI */ + COSTS_N_INSNS (51), /* SI */ + COSTS_N_INSNS (83), /* DI */ + COSTS_N_INSNS (83)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 9, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {3, 4, 3}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {3, 4, 3}, /* cost of storing integer registers */ + 4, /* cost of reg,reg fld/fst */ + {4, 4, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {6, 6, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 2, /* cost of moving MMX register */ + {3, 3}, /* cost of loading MMX registers + in SImode and DImode */ + {4, 4}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {4, 4, 3}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {4, 4, 5}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 3, /* MMX or SSE register to integer */ + /* On K8: + MOVD reg64, xmmreg Double FSTORE 4 + MOVD reg32, xmmreg Double FSTORE 4 + On AMDFAM10: + MOVD reg64, xmmreg Double FADD 3 + 1/1 1/1 + MOVD reg32, xmmreg Double FADD 3 + 1/1 1/1 */ + 32, /* size of l1 cache. */ + 2048, /* size of l2 cache. */ + 64, /* size of prefetch block */ + 100, /* number of parallel prefetches */ + 2, /* Branch cost */ + COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (4), /* cost of FMUL instruction. */ + COSTS_N_INSNS (19), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (35), /* cost of FSQRT instruction. */ + + {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}}, + {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + {{libcall, {{8, loop}, {24, unrolled_loop}, + {2048, rep_prefix_4_byte}, {-1, libcall}}}, + {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + 4, /* scalar_stmt_cost. */ + 2, /* scalar load_cost. */ + 2, /* scalar_store_cost. */ + 6, /* vec_stmt_cost. */ + 0, /* vec_to_scalar_cost. */ + 2, /* scalar_to_vec_cost. */ + 2, /* vec_align_load_cost. */ + 2, /* vec_unalign_load_cost. */ + 2, /* vec_store_cost. */ + 2, /* cond_taken_branch_cost. */ + 1, /* cond_not_taken_branch_cost. */ +}; + static const struct processor_costs pentium4_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ @@ -1904,8 +1983,10 @@ const struct processor_costs *ix86_cost #define m_BDVER1 (1<<PROCESSOR_BDVER1) #define m_BDVER2 (1<<PROCESSOR_BDVER2) #define m_BDVER (m_BDVER1 | m_BDVER2) +#define m_BTVER (m_BTVER1 | m_BTVER2) #define m_BTVER1 (1<<PROCESSOR_BTVER1) -#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1) +#define m_BTVER2 (1<<PROCESSOR_BTVER2) +#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER) #define m_GENERIC32 (1<<PROCESSOR_GENERIC32) #define m_GENERIC64 (1<<PROCESSOR_GENERIC64) @@ -1945,7 +2026,7 @@ static unsigned int initial_ix86_tune_fe ~m_386, /* X86_TUNE_USE_SAHF */ - m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC, + m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC, /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid partial dependencies. */ @@ -2047,7 +2128,7 @@ static unsigned int initial_ix86_tune_fe m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC, /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */ - m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER1, + m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER, /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */ m_COREI7 | m_BDVER, @@ -2122,11 +2203,11 @@ static unsigned int initial_ix86_tune_fe /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is vector path on AMD machines. */ - m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC64, + m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC64, /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD machines. */ - m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC64, + m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC64, /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR than a MOV. */ @@ -2599,6 +2680,7 @@ static const struct ptt processor_target {&bdver1_cost, 32, 24, 32, 7, 32}, {&bdver2_cost, 32, 24, 32, 7, 32}, {&btver1_cost, 32, 24, 32, 7, 32}, + {&btver2_cost, 32, 24, 32, 7, 32}, {&atom_cost, 16, 15, 16, 7, 16} }; @@ -2629,7 +2711,8 @@ static const char *const cpu_names[TARGE "amdfam10", "bdver1", "bdver2", - "btver1" + "btver1", + "btver2" }; /* Return true if a red-zone is in use. */ @@ -3056,6 +3139,11 @@ ix86_option_override_internal (bool main {"btver1", PROCESSOR_BTVER1, CPU_GENERIC64, PTA_64BIT | PTA_MMX | PTA_PREFETCHW | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16}, + {"btver2", PROCESSOR_BTVER2, CPU_GENERIC64, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1 + | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX + | PTA_BMI | PTA_F16C | PTA_MOVBE}, {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO, 0 /* flags are only used for -march switch. */ }, {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64, @@ -23692,6 +23780,7 @@ ix86_issue_rate (void) case PROCESSOR_PENTIUM: case PROCESSOR_ATOM: case PROCESSOR_K6: + case PROCESSOR_BTVER2: return 2; case PROCESSOR_PENTIUMPRO: @@ -23898,6 +23987,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt case PROCESSOR_BDVER1: case PROCESSOR_BDVER2: case PROCESSOR_BTVER1: + case PROCESSOR_BTVER2: case PROCESSOR_ATOM: case PROCESSOR_GENERIC32: case PROCESSOR_GENERIC64: Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi.orig 2013-01-17 17:25:35.000000000 +0100 +++ gcc/doc/invoke.texi 2013-01-17 17:35:45.000000000 +0100 @@ -13291,6 +13291,10 @@ extensions.) AMD Family 14h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set extensions.) +@item btver2 +CPUs based on AMD Family 16h cores with x86-64 instruction set support. This +includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, +SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions. @item winchip-c6 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction set support.