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File mozilla-ppc-ipc.patch of Package firefox5
# HG changeset patch # Parent f6996f95c7f8007fd7bf759092488ead6843441a Bug 587188 - Failed to build firefox from trunk on PPC (fixed m-c) diff --git a/ipc/chromium/Makefile.in b/ipc/chromium/Makefile.in --- a/ipc/chromium/Makefile.in +++ b/ipc/chromium/Makefile.in @@ -241,17 +241,16 @@ CPPSRCS += \ endif # } OS_MACOSX ifdef OS_LINUX # { CPPSRCS += \ atomicops_internals_x86_gcc.cc \ base_paths_linux.cc \ - data_pack.cc \ file_util_linux.cc \ file_version_info_linux.cc \ idle_timer_none.cc \ process_util_linux.cc \ time_posix.cc \ $(NULL) ifdef MOZ_ENABLE_GTK2 diff --git a/ipc/chromium/src/base/atomicops.h b/ipc/chromium/src/base/atomicops.h --- a/ipc/chromium/src/base/atomicops.h +++ b/ipc/chromium/src/base/atomicops.h @@ -127,13 +127,15 @@ Atomic64 Release_Load(volatile const Ato #if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY) #include "base/atomicops_internals_x86_msvc.h" #elif defined(OS_MACOSX) && defined(ARCH_CPU_X86_FAMILY) #include "base/atomicops_internals_x86_macosx.h" #elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY) #include "base/atomicops_internals_x86_gcc.h" #elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY) #include "base/atomicops_internals_arm_gcc.h" +//#elif defined(COMPILER_GCC) && defined(ARCH_CPU_PPC_FAMILY) +//#include "base/atomicops_internals_ppc_gcc.h" #else #include "base/atomicops_internals_mutex.h" #endif #endif // BASE_ATOMICOPS_H_ diff --git a/ipc/chromium/src/base/atomicops_internals_ppc_gcc.h b/ipc/chromium/src/base/atomicops_internals_ppc_gcc.h new file mode 100644 --- /dev/null +++ b/ipc/chromium/src/base/atomicops_internals_ppc_gcc.h @@ -0,0 +1,148 @@ +// Copyright (c) 2010 JJDaNiMoTh <jjdanimoth@gmail.com>. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. + +// This file is an internal atomic implementation, use base/atomicops.h instead. + +#ifndef BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_ +#define BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_ +#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory") + +#define PPC_ACQUIRE_BARRIER "\nisync\n" +#define PPC_RELEASE_BARRIER "\nlwsync\n" + +namespace base { +namespace subtle { + +// 32-bit low-level operations on any platform. + +/* + * Compare and exchange - if *ptr == old, set it to new, + * and return the old value of *p. + */ +inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, + Atomic32 old_value, + Atomic32 new_value) { + Atomic32 prev; + + __asm__ __volatile__ ( + "1: lwarx %0,0,%2\n" + "cmpw 0,%0,%3\n" + "bne- 2f\n" + "stwcx. %4,0,%2\n" + "bne- 1b\n" + "2:\n" + : "=&r" (prev), "+m" (*ptr) + : "r" (ptr), "r" (old_value), "r" (new_value) + : "cc", "memory"); + + return prev; +} + +/* +* Atomic exchange +* +* Changes the memory location '*ptr' to be new_value and returns +* the previous value stored there. +*/ +inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, + Atomic32 new_value) { + Atomic32 prev; + + __asm__ __volatile__( +"1: lwarx %0,0,%2 \n" +" stwcx. %3,0,%2 \n\ + bne- 1b" + : "=&r" (prev), "+m" (*ptr) + : "r" (ptr), "r" (new_value) + : "cc", "memory"); + + return prev; +} + +inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, + Atomic32 increment) { + Atomic32 temp; + + __asm__ __volatile__( +"1: lwarx %0,0,%2\n\ + add %0,%1,%0\n" +" stwcx. %0,0,%2 \n\ + bne- 1b" + : "=&r" (temp) + : "r" (increment), "r" (ptr) + : "cc", "memory"); + + return temp; +} + +inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, + Atomic32 increment) { + Atomic32 temp; + + __asm__ __volatile__( + PPC_RELEASE_BARRIER +"1: lwarx %0,0,%2\n\ + add %0,%1,%0\n" +" stwcx. %0,0,%2 \n\ + bne- 1b" + PPC_ACQUIRE_BARRIER + : "=&r" (temp) + : "r" (increment), "r" (ptr) + : "cc", "memory"); + + return temp; +} + +inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, + Atomic32 old_value, + Atomic32 new_value) { + return NoBarrier_CompareAndSwap(ptr, old_value, new_value); +} + +inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, + Atomic32 old_value, + Atomic32 new_value) { + return NoBarrier_CompareAndSwap(ptr, old_value, new_value); +} + +inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) { + *ptr = value; +} + +inline void MemoryBarrier() { + __asm__ __volatile__("sync" : : : "memory"); +} + +inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) { + *ptr = value; + MemoryBarrier(); +} + +inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) { + MemoryBarrier(); + *ptr = value; +} + +inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) { + return *ptr; +} + +inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) { + Atomic32 value = *ptr; + MemoryBarrier(); + return value; + +} + +inline Atomic32 Release_Load(volatile const Atomic32* ptr) { + MemoryBarrier(); + return *ptr; +} + +} // namespace base::subtle +} // namespace base + +#undef ATOMICOPS_COMPILER_BARRIER + +#endif // BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_ diff --git a/ipc/chromium/src/build/build_config.h b/ipc/chromium/src/build/build_config.h --- a/ipc/chromium/src/build/build_config.h +++ b/ipc/chromium/src/build/build_config.h @@ -52,19 +52,20 @@ #define ARCH_CPU_X86_FAMILY 1 #define ARCH_CPU_X86 1 #define ARCH_CPU_32_BITS 1 #elif defined(__ARMEL__) #define ARCH_CPU_ARM_FAMILY 1 #define ARCH_CPU_ARMEL 1 #define ARCH_CPU_32_BITS 1 #define WCHAR_T_IS_UNSIGNED 1 -#elif defined(__ppc__) +#elif defined(__ppc__) || defined(__powerpc) || defined(__PPC__) #define ARCH_CPU_PPC 1 #define ARCH_CPU_32_BITS 1 +#define ARCH_CPU_PPC_FAMILY 1 #else #error Please add support for your architecture in build/build_config.h #endif // Type detection for wchar_t. #ifndef CHROMIUM_MOZILLA_BUILD #if defined(OS_WIN)
