|
[-]
[+]
|
Deleted |
x86info.changes
|
| @@ -1,30 +0,0 @@
--------------------------------------------------------------------
-Tue May 27 07:40:00 CEST 2008 - cs@linux-administrator.com
-
-- update to version 1.21
-
--------------------------------------------------------------------
-Tue Sep 11 22:27:12 CEST 2007 - bwalle@suse.de
-
-- update to version 1.20
-
--------------------------------------------------------------------
-Fri Jul 26 17:37:08 CEST 2002 - rommel@suse.de
-
-- Update to version 1.10 (see ChangeLog for full list of changes)
-
--------------------------------------------------------------------
-Thu Dec 20 14:01:28 CET 2001 - grimmer@suse.de
-
-- Update to version 1.7 (see ChangeLog for full list of changes)
-
--------------------------------------------------------------------
-Thu Nov 22 12:38:04 CET 2001 - grimmer@suse.de
-
-- Update to version 1.6 (see ChangeLog for full list of changes)
-
--------------------------------------------------------------------
-Tue Aug 28 09:29:39 CEST 2001 - grimmer@suse.de
-
-- Initial package for SuSE Linux (Version 1.5)
-
|
|
[-]
[+]
|
Changed |
x86info.spec
^
|
|
|
|
|
Deleted |
ready
^
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT
^
|
| -(directory)
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/IDT.h
^
|
| @@ -1,6 +0,0 @@
-#ifndef _IDT_H
-#define _IDT_H
-void dump_C3_MSR (struct cpudata *cpu);
-void decode_longhaul(struct cpudata *cpu);
-void decode_powersaver(struct cpudata *cpu);
-#endif /* _IDT_H */
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/MSR-C3.c
^
|
| @@ -1,32 +0,0 @@
-/*
- * $Id: MSR-C3.c,v 1.5 2003/11/04 01:36:43 davej Exp $
- * This file is part of x86info.
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * IDT/Centaur specific parts.
- */
-#include <stdio.h>
-#include "../x86info.h"
-#include "IDT.h"
-
-void dump_C3_MSR (struct cpudata *cpu)
-{
- if (!user_is_root)
- return;
-
- printf ("FCR: ");
- dumpmsr (cpu->number, 0x1107, 32);
-
- printf ("Power management: ");
- if (cpu->model==6 || cpu->model==7) {
- printf ("Longhaul\n");
- decode_longhaul(cpu);
- }
-
- if (cpu->model==8 || cpu->model==9) {
- printf ("Powersaver\n");
- decode_powersaver(cpu);
- }
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/identify.c
^
|
| @@ -1,194 +0,0 @@
-/*
- * $Id: identify.c,v 1.33 2004/08/11 11:18:27 davej Exp $
- * This file is part of x86info.
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * IDT/Centaur specific parts.
- */
-#include <stdio.h>
-#include "../x86info.h"
-#include "IDT.h"
-
-static char *idt_nameptr;
-#define add_to_cpuname(x) idt_nameptr += snprintf(idt_nameptr, sizeof(x), "%s", x);
-
-void Identify_IDT(struct cpudata *cpu)
-{
- char *nameptr;
- unsigned long eax, ebx, ecx, edx;
-
- idt_nameptr = nameptr = cpu->name;
-
- cpu->vendor = VENDOR_CENTAUR;
-
- /* Do standard stuff */
- if (cpu->maxi < 1)
- return;
-
- cpuid(cpu->number, 1, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
-
- switch (tuple(cpu) & 0xff0) {
- case 0x540:
- add_to_cpuname("Winchip C6");
- //transistors = 5400000;
- //fab_process = "0.35 micron CMOS";
- //die_size = "88 sq.mm";
- //introduction_date = "September 1997";
- //pipeline_stages = 6;
- break;
- case 0x580:
- switch (cpu->stepping) {
- case 0 ... 6:
- add_to_cpuname("Winchip 2");
- break;
- case 7 ... 9:
- add_to_cpuname("Winchip 2A");
- break;
- case 0xA ... 0xF:
- add_to_cpuname("Winchip 2B");
- break;
- }
- break;
- case 0x590:
- add_to_cpuname("Winchip 3");
- break;
-
- /* Family 6 is when VIA bought out Cyrix & IDT
- * This is the CyrixIII family. */
- case 0x660:
- add_to_cpuname("VIA Cyrix 3 (Samuel) [C5A]");
- //pipeline_stages = 12;
- //1.8-2.0V
- //CPGA
- //75mm
- //0.18 Al
- //500-733MHz
- //11.3 mil transistors
- //June 6 2000
- break;
- case 0x670:
- switch (cpu->stepping) {
- case 0 ... 7:
- add_to_cpuname("VIA C3 (Samuel 2) [C5B]");
- //pipeline_stages = 12;
- //1.6V
- //CPGA/EBGA
- //52mm
- //0.15u Al
- //650-800MHz
- //15.2 mil transistors
- //Mar 25 2001
- break;
- case 8 ... 0xf:
- add_to_cpuname("VIA C3 (Ezra) [C5C]");
- //pipeline_stages = 12;
- //1.35V
- //CPGA/EBGA
- //52mm
- //0.15u/0.13u hybrid Al
- //800-1000MHz
- //15.4 mil transistors
- //Sep 11 2001
- break;
- }
- break;
- /* Ezra-T is much like Ezra but reworked to run in Pentium III Tualatin sockets. */
- case 0x680: add_to_cpuname("VIA C3 (Ezra-T) [C5M/C5N]");
- //pipeline_stages = 12;
- //CPGA/EBGA/uPGA2/uFCPGA
- //900-1200MHz
- //56mm
- //0.15/0.13u hybrid (Cu)
- //15.5 mil transistors
- //C5N=copper interconnectrs
- //2002
- break;
- case 0x690: add_to_cpuname("VIA C3 (Nehemiah) [C5XL]");
- //pipeline_stages = 16;
- //2 SSE units
- //first C3 to run FPU at full clock speed (previous ran at 50%)
- //1100-1300
- //0.13 (Cu)
- //die_size = "78 sq. mm"; (C5X)
- //die_size = "54 sq. mm"; (C5XL)
- //January 22 2003
- break;
- case 0x6A0: switch (cpu->stepping) {
- case 0:
- case 8 ... 0xF:
- add_to_cpuname("VIA C3 (Esther) [C7-M]");
- break;
- case 1 ... 7:
- add_to_cpuname("VIA C3 (Ruth) [C7-M]");
- break;
- }
- break;
-
- // C5P introduced the HW AES
- // C5YL
- // C5X
- // CZA
-
- default:
- add_to_cpuname("Unknown VIA CPU");
- break;
- }
-}
-
-
-void decode_IDT_cacheinfo(struct cpudata *cpu)
-{
- unsigned long eax, ebx, ecx, edx;
-
- if (cpu->maxei >= 0x80000005) {
- /* TLB and cache info */
- cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx);
- printf("Cache info\n");
- printf(" L1 Instruction cache: %ldKB, %ld-way associative, %ld lines per tag, line size=%ld bytes.\n",
- edx >> 24, (edx >> 16) & 0xff, (edx >> 8) & 0xff, edx & 0xff);
- printf(" L1 Data cache: %ldKB %ld-way associative, %ld lines per tag, line size=%ld bytes.\n",
- ecx >> 24, (ecx >> 16) & 0xff, (ecx >> 8) & 0xff, ecx & 0xff);
- if (cpu->maxei >= 0x80000006) {
- cpuid (cpu->number, 0x80000006, &eax, &ebx, &ecx, &edx);
- if ((cpu->family==6) && (cpu->model==7 || cpu->model==8))
- /* Work around errata. */
- printf (" L2 (on CPU) cache: %ldKB %ld-way associative, %ld lines per tag, line size=%ld bytes.\n",
- ecx >> 24, (ecx >> 16) & 0x0f, (ecx >> 8) & 0x0f, ecx & 0xff);
- else
- printf (" L2 (on CPU) cache: %ldKB %ld-way associative, %ld lines per tag, line size=%ld bytes.\n",
- ecx >> 16, (ecx >> 12) & 0x0f, (ecx >> 8) & 0x0f, ecx & 0xff);
- }
- printf("TLB info\n");
- cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx);
- printf(" Instruction TLB: %ld-way associative. %ld entries.\n", (ebx >> 8) & 0xff, ebx & 0xff);
- printf(" Data TLB: %ld-way associative. %ld entries.\n", ebx >> 24, (ebx >> 16) & 0xff);
- }
-
- /* check on-chip L2 cache size */
-}
-
-
-void display_IDT_info(struct cpudata *cpu)
-{
- printf("Family: %u Model: %u Stepping: %u\n",
- cpu->family, cpu->model, cpu->stepping);
- printf ("CPU Model : %s\n", cpu->name);
- get_model_name (cpu);
-
-
- /* Check for presence of extended info */
- decode_feature_flags(cpu);
-
- if (cpu->maxei == 0)
- return;
-
- decode_IDT_cacheinfo(cpu);
-
- if (cpu->family == 6 && show_registers)
- dump_C3_MSR(cpu);
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/longhaul-v2.c
^
|
| @@ -1,86 +0,0 @@
-/*
- * $Id: longhaul-v2.c,v 1.3 2003/07/15 19:04:53 davej Exp $
- * This file is part of x86info.
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * IDT/Centaur specific parts.
- */
-#include <stdio.h>
-#include "../x86info.h"
-
-union msr_longhaul {
- struct {
- unsigned RevisionID:4, // 3:0
- RevisionKey:4, // 7:4
- EnableSoftBusRatio:1, // 8
- EnableSoftVID:1, // 9
- EnableSoftBSEL:1, // 10
- Reserved:3, // 11:13
- SoftBusRatio4:1, // 14
- VRMRev:1, // 15
- SoftBusRatio:4, // 19:16
- SoftVID:5, // 24:20
- Reserved2:3, // 27:25
- SoftBSEL:2, // 29:28
- Reserved3:2, // 31:30
- MaxMHzBR:4, // 35:32
- MaximumVID:5, // 40:36
- MaxMHzFSB:2, // 42:41
- MaxMHzBR4:1, // 43
- Reserved4:4, // 47:44
- MinMHzBR:4, // 51:48
- MinimumVID:5, // 56:52
- MinMHzFSB:2, // 58:57
- MinMHzBR4:1, // 59
- Reserved5:4; // 63:60
- } bits;
- unsigned long long val;
-};
-
-void decode_longhaul2(struct cpudata *cpu)
-{
- union msr_longhaul longhaul;
-
- if (read_msr(cpu->number, 0x110A, &longhaul.val) == 1) {
- dumpmsr (cpu->number, 0x110A, 64);
-
- if (longhaul.bits.RevisionID & 1)
- printf ("\tSoftVID support\n");
- if (longhaul.bits.RevisionID & 2)
- printf ("\tSoftBSEL support\n");
- if (longhaul.bits.RevisionID == 0)
- printf ("\tSoftware clock multiplier only: No Softvid\n");
-
- if (longhaul.bits.EnableSoftBusRatio==1)
- printf ("\tEnableSoftBusRatio=Enabled\n");
- if (longhaul.bits.EnableSoftVID==1)
- printf ("\tEnableSoftVID=Enabled\n");
- if (longhaul.bits.EnableSoftBSEL==1)
- printf ("\tEnableSoftBSEL=Enabled\n");
-
- printf ("\tSoftBusRatio4=%s\n", longhaul.bits.SoftBusRatio4 ? "1" : "0");
- printf ("\tSoftBusRatio=");
- binary (4, longhaul.bits.SoftBusRatio);
-
- if (longhaul.bits.RevisionID & 1)
- printf ("\tVRM Rev=%s\n",
- longhaul.bits.VRMRev ? "Mobile VRM" : "VRM 8.5");
-
- printf ("\tMaxMHzBR4: %s\n", longhaul.bits.MaxMHzBR4 ? "1" : "0");
- printf ("\tMaxMHzBR: ");
- binary (4, longhaul.bits.MaxMHzBR);
- printf ("\tMaximumVID: ");
- binary (5, longhaul.bits.MaximumVID);
- printf ("\tMaxMHzFSB: ");
- binary (2, longhaul.bits.MaxMHzFSB);
- printf ("\tMinMHzBR4: %s\n", longhaul.bits.MinMHzBR4 ? "1" : "0");
- printf ("\tMinMHzBR: ");
- binary (4, longhaul.bits.MinMHzBR);
- printf ("\tMinimumVID: ");
- binary (4, longhaul.bits.MinimumVID);
- printf ("\tMinMHzFSB: ");
- binary (2, longhaul.bits.MinMHzFSB);
- }
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/longhaul.c
^
|
| @@ -1,86 +0,0 @@
-/*
- * $Id: longhaul.c,v 1.1 2003/11/04 01:36:43 davej Exp $
- * This file is part of x86info.
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * IDT/Centaur specific parts.
- */
-#include <stdio.h>
-#include "../x86info.h"
-
-union msr_longhaul {
- struct {
- unsigned RevisionID:4, // 3:0
- RevisionKey:4, // 7:4
- EnableSoftBusRatio:1, // 8
- EnableSoftVID:1, // 9
- EnableSoftBSEL:1, // 10
- Reserved:3, // 11:13
- SoftBusRatio4:1, // 14
- VRMRev:1, // 15
- SoftBusRatio:4, // 19:16
- SoftVID:5, // 24:20
- Reserved2:3, // 27:25
- SoftBSEL:2, // 29:28
- Reserved3:2, // 31:30
- MaxMHzBR:4, // 35:32
- MaximumVID:5, // 40:36
- MaxMHzFSB:2, // 42:41
- MaxMHzBR4:1, // 43
- Reserved4:4, // 47:44
- MinMHzBR:4, // 51:48
- MinimumVID:5, // 56:52
- MinMHzFSB:2, // 58:57
- MinMHzBR4:1, // 59
- Reserved5:4; // 63:60
- } bits;
- unsigned long long val;
-};
-
-void decode_longhaul(struct cpudata *cpu)
-{
- union msr_longhaul longhaul;
-
- if (read_msr(cpu->number, 0x110A, &longhaul.val) == 1) {
- dumpmsr (cpu->number, 0x110A, 64);
-
- if (longhaul.bits.RevisionID & 1)
- printf ("\tSoftVID support\n");
- if (longhaul.bits.RevisionID & 2)
- printf ("\tSoftBSEL support\n");
- if (longhaul.bits.RevisionID == 0)
- printf ("\tSoftware clock multiplier only: No Softvid\n");
-
- if (longhaul.bits.EnableSoftBusRatio==1)
- printf ("\tEnableSoftBusRatio=Enabled\n");
- if (longhaul.bits.EnableSoftVID==1)
- printf ("\tEnableSoftVID=Enabled\n");
- if (longhaul.bits.EnableSoftBSEL==1)
- printf ("\tEnableSoftBSEL=Enabled\n");
-
- printf ("\tSoftBusRatio4=%s\n", longhaul.bits.SoftBusRatio4 ? "1" : "0");
- printf ("\tSoftBusRatio=");
- binary (4, longhaul.bits.SoftBusRatio);
-
- if (longhaul.bits.RevisionID & 1)
- printf ("\tVRM Rev=%s\n",
- longhaul.bits.VRMRev ? "Mobile VRM" : "VRM 8.5");
-
- printf ("\tMaxMHzBR4: %s\n", longhaul.bits.MaxMHzBR4 ? "1" : "0");
- printf ("\tMaxMHzBR: ");
- binary (4, longhaul.bits.MaxMHzBR);
- printf ("\tMaximumVID: ");
- binary (5, longhaul.bits.MaximumVID);
- printf ("\tMaxMHzFSB: ");
- binary (2, longhaul.bits.MaxMHzFSB);
- printf ("\tMinMHzBR4: %s\n", longhaul.bits.MinMHzBR4 ? "1" : "0");
- printf ("\tMinMHzBR: ");
- binary (4, longhaul.bits.MinMHzBR);
- printf ("\tMinimumVID: ");
- binary (4, longhaul.bits.MinimumVID);
- printf ("\tMinMHzFSB: ");
- binary (2, longhaul.bits.MinMHzFSB);
- }
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/powersaver.c
^
|
| @@ -1,87 +0,0 @@
-/*
- * $Id: powersaver.c,v 1.3 2003/11/04 01:36:43 davej Exp $
- * This file is part of x86info.
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * C3 specific information
- *
- */
-
-#include <stdio.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include "../x86info.h"
-#include "IDT.h"
-#include "powersaver.h"
-
-void decode_powersaver(struct cpudata *cpu)
-{
- union msr_powersaver ps;
-
- if (!user_is_root)
- return;
-
- dumpmsr(cpu->number, MSR_POWERSAVER, 64);
- printf("\n");
-
- if (read_msr(cpu->number, MSR_POWERSAVER, &ps.val) != 1) {
- printf ("Something went wrong reading MSR_POWERSAVER\n");
- return;
- }
-
- printf (" RevisionID: %x : ", ps.bits.RevisionID);
- switch (ps.bits.RevisionID) {
- case 0x0: printf ("Initial revision (Software clock multiplier only, no SoftVID)\n");
- break;
- case 0x1: printf ("SoftVID support\n");
- break;
- default: printf ("Unknown (0x%x).\n", ps.bits.RevisionID);
- break;
- }
-
- printf (" Software clock multiplier is ");
- if (ps.bits.EnableSoftBusRatio == 0)
- printf ("disabled\n");
- else {
- printf ("enabled\n");
- printf ("\tMaxMHzBR4: %s\n", ps.bits.MaxMHzBR4 ? "1" : "0");
- printf ("\tMaxMHzBR: ");
- binary (4, ps.bits.MaxMHzBR);
- printf ("\tMinMHzBR4: %s\n", ps.bits.MinMHzBR4 ? "1" : "0");
- printf ("\tMinMHzBR: ");
- binary (4, ps.bits.MinMHzBR);
- }
-
- /* these bits invalid if revision == 0*/
- if (ps.bits.RevisionID != 0) {
- printf (" Software VID is ");
- if (ps.bits.EnableSoftVID == 0)
- printf ("disabled\n");
- else {
- printf ("enabled\n");
- printf ("\tVRM Rev=%s\n",
- ps.bits.VRMRev ? "Mobile VRM" : "VRM 8.5");
- printf ("\tMinimumVID: ");
- binary (4, ps.bits.MinimumVID);
- printf ("\tMaximumVID: ");
- binary (5, ps.bits.MaximumVID);
- }
-
- if (ps.bits.EnableSoftBusRatio==1) {
- printf ("\tEnableSoftBusRatio=Enabled\n");
- printf ("\tMaxMHzFSB: ");
- binary (2, ps.bits.MaxMHzFSB);
- printf ("\tMinMHzFSB: ");
- binary (2, ps.bits.MinMHzFSB);
- }
-
- //if (ps.bits.EnableSoftBSEL==1)
- // printf ("\tEnableSoftBSEL=Enabled\n");
-
- printf ("\tSoftBusRatio4=%s\n", ps.bits.SoftBusRatio4 ? "1" : "0");
- printf ("\tSoftBusRatio=");
- binary (4, ps.bits.SoftBusRatio);
- }
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/IDT/powersaver.h
^
|
| @@ -1,41 +0,0 @@
-/*
- * $Id: powersaver.h,v 1.1 2003/01/27 17:33:16 davej Exp $
- * This file is part of x86info.
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * AMD-specific information
- *
- */
-
-#include <sys/types.h>
-
-#define MSR_POWERSAVER 0x110a
-
-union msr_powersaver {
- struct {
- unsigned RevisionID:4, // 3:0
- RevisionKey:4, // 7:4
- EnableSoftBusRatio:1, // 8
- EnableSoftVID:1, // 9
- Reserved:4, // 10:13
- SoftBusRatio4:1, // 14
- VRMRev:1, // 15
- SoftBusRatio:4, // 16:19
- SoftVID:5, // 20:24
- Reserved2:7, // 25:31
- MaxMHzBR:4, // 32:35
- MaximumVID:5, // 36:40
- MaxMHzFSB:2, // 41:42
- MaxMHzBR4:1, // 43
- Reserved3:4, // 44:47
- MinMHzBR:4, // 48:51
- MinimumVID:5, // 52:56
- MinMHzFSB:2, // 57:58
- MinMHzBR4:1, // 59
- Reserved4:4; // 60:63
- } bits;
- unsigned long long val;
-};
-
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/cpuid_UP.S
^
|
| @@ -1,81 +0,0 @@
- .align 4
- .text
-
-.globl cpuid_UP
- .type cpuid_UP,@function
-cpuid_UP:
-
-#ifdef __x86_64__
-/* x86_64 calling convention: Args passed in rdi, rsi, rdx, rcx, r8, r9;
- rbc, r12 -- r15, and rbp need to be preserved. */
- pushq %rbp
- movq %rsp,%rbp
- pushq %rbx
- movq %rdx, %r10
- movq %rcx, %r11
- movq %rdi, %rax
- cpuid
- test %rsi,%rsi
- jz L1
- movq %rax,(%rsi)
-
-L1:
- test %r10,%r10
- jz L2
- movq %rbx,(%r10)
-
-L2:
- test %r11,%r11
- jz L3
- movq %rcx,(%r11)
-
-L3:
- test %r8,%r8
- jz L4
- movq %rdx,(%r8)
-
-L4:
- popq %rbx
- movq %rbp,%rsp
- popq %rbp
- ret
-#else
- pushl %ebp
- movl %esp,%ebp
- pushl %edi
- pushl %ebx
- pushl %ecx
- pushl %edx
- movl 8(%ebp),%eax
- cpuid
- movl 12(%ebp),%edi
- test %edi,%edi
- jz L1
- movl %eax,(%edi)
-
-L1: movl 16(%ebp),%edi
- test %edi,%edi
- jz L2
- movl %ebx,(%edi)
-
-L2: movl 20(%ebp),%edi
- test %edi,%edi
- jz L3
- movl %ecx,(%edi)
-
-L3: movl 24(%ebp),%edi
- test %edi,%edi
- jz L4
- movl %edx,(%edi)
-
-L4: popl %edx
- popl %ecx
- popl %ebx
- popl %edi
- movl %ebp,%esp
- popl %ebp
- ret
-#endif
-
-.section .note.GNU-stack,"", @progbits
-
|
|
[-]
[+]
|
Deleted |
x86info-1.21.tgz/results/VIA
^
|
| -(directory)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/.gitignore
^
|
| @@ -1,2 +1,7 @@
*.o
+*.P
x86info
+AMD/fam10h.h
+AMD/k8.h
+generic_msr.h
+lsmsr
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/AMD.h
^
|
| @@ -1,3 +1,11 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * AMD specific prototypes.
+ */
+
#ifndef _AMD_H
#define _AMD_H
extern void decode_athlon_bluesmoke(int cpunum);
@@ -5,7 +13,7 @@
extern void dump_k6_MSR (struct cpudata *cpu);
extern void decode_powernow (struct cpudata *cpu);
extern void show_amd_bugs(struct cpudata *cpu);
-extern void dump_PSB(struct cpudata *cpu, int maxfid, int startvid);
+extern void dump_PSB(struct cpudata *cpu, unsigned int maxfid, unsigned int startvid);
#define MSR_CLKCTL 0xc001001b
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/MSR-Athlon.c
^
|
| @@ -1,12 +1,9 @@
/*
- * $Id: MSR-Athlon.c,v 1.5 2002/12/04 18:07:03 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* AMD-Athlon specific MSR information
- *
*/
#include <stdio.h>
@@ -25,5 +22,5 @@
dumpmsr(cpu->number, 0xC0010010, 32);
dumpmsr(cpu->number, 0xC0010015, 32);
dumpmsr(cpu->number, MSR_CLKCTL, 32);
- printf ("\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/MSR-K6.c
^
|
| @@ -1,13 +1,10 @@
/*
- * $Id: MSR-K6.c,v 1.10 2002/11/25 15:34:30 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* AMD-K6 specific MSR information
* See 21329h1.pdf for more details.
- *
*/
#include <stdio.h>
@@ -26,53 +23,53 @@
dumpmsr(cpu->number, 0xC0000082, 32);
/* Original K6 or K6-2 (old core). */
- if ((cpu->model < 8) || ((cpu->model==8) && (cpu->stepping <8))) {
+ if ((cpu->model < 8) || ((cpu->model == 8) && (cpu->stepping < 8))) {
if (read_msr (cpu->number, 0xC0000082, &val) == 1) {
- printf ("Write allocate enable limit: %dMbytes\n", (int) ((val & 0x7e) >>1) * 4);
- printf ("Write allocate 15-16M bytes: %s\n", val & 1 ? "enabled" : "disabled");
+ printf("Write allocate enable limit: %dMbytes\n", (int) ((val & 0x7e) >>1) * 4);
+ printf("Write allocate 15-16M bytes: %s\n", val & 1 ? "enabled" : "disabled");
} else {
- printf ("Couldn't read WHCR register.\n");
+ printf("Couldn't read WHCR register.\n");
}
}
/* K6-2 core (Stepping 8-F), K6-III or later. */
- if ((cpu->model > 8) || ((cpu->model==8) && (cpu->stepping>=8))) {
+ if ((cpu->model > 8) || ((cpu->model == 8) && (cpu->stepping >= 8))) {
if (read_msr (cpu->number, 0xC0000082, &val) == 1) {
if (!(val & (0x3ff << 22)))
- printf ("Write allocate disabled\n");
+ printf("Write allocate disabled\n");
else {
- printf ("Write allocate enable limit: %dMbytes\n", (int) ((val >> 22) & 0x3ff) * 4);
- printf ("Write allocate 15-16M bytes: %s\n", val & (1<<16) ? "enabled" : "disabled");
+ printf("Write allocate enable limit: %dMbytes\n", (int) ((val >> 22) & 0x3ff) * 4);
+ printf("Write allocate 15-16M bytes: %s\n", val & (1<<16) ? "enabled" : "disabled");
}
} else {
- printf ("Couldn't read WHCR register.\n");
+ printf("Couldn't read WHCR register.\n");
}
}
/* Dump EWBE register on K6-2 & K6-3 */
- if ((cpu->family==5) && (cpu->model>=8)) {
+ if ((cpu->family == 5) && (cpu->model >= 8)) {
if (read_msr (cpu->number, 0xC0000080, &val) == 1) {
if (val & (1<<0))
- printf ("System call extension present.\n");
+ printf("System call extension present.\n");
if (val & (1<<1))
- printf ("Data prefetch enabled.\n");
+ printf("Data prefetch enabled.\n");
else
- printf ("Data prefetch disabled.\n");
- printf ("EWBE mode: ");
+ printf("Data prefetch disabled.\n");
+ printf("EWBE mode: ");
switch ((val & (1<<2|1<<3|1<<4))>>2) {
- case 0: printf ("strong ordering (slowest performance)\n");
+ case 0: printf("strong ordering (slowest performance)\n");
break;
- case 1: printf ("speculative disable (close to best performance)\n");
+ case 1: printf("speculative disable (close to best performance)\n");
break;
- case 2: printf ("invalid\n");
+ case 2: printf("invalid\n");
break;
- case 3: printf ("global disable (best performance)\n");
+ case 3: printf("global disable (best performance)\n");
break;
}
} else {
- printf ("Couldn't read EFER register.\n");
+ printf("Couldn't read EFER register.\n");
}
}
- printf ("\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/bluesmoke.c
^
|
| @@ -1,18 +1,16 @@
/*
- * $Id: bluesmoke.c,v 1.6 2003/04/11 00:17:19 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
- * Dump MCA registers.
- *
+ * Dump machine check registers.
*/
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include "../x86info.h"
+#include "AMD.h"
#define MCG_CAP 0x0179
#define MCG_STATUS 0x17a
@@ -35,87 +33,87 @@
return;
if ((val & (1<<8)) == 0)
- printf ("Erk, MCG_CTL not present! :%016llx:\n", val);
+ printf("Erk, MCG_CTL not present! :%016llx:\n", val);
banks = val & 0xf;
- printf ("Number of reporting banks : %d\n\n", banks);
+ printf("Number of reporting banks : %d\n\n", banks);
if (read_msr(cpunum, MCG_STATUS, &val) == 1) {
if (val != 0) {
printf(" 31 23 15 7 \n");
- printf ("MCG_STATUS: ");
+ printf("MCG_STATUS: ");
dumpmsr_bin (cpunum, MCG_STATUS, 32);
}
}
if (read_msr(cpunum, MCG_CTL, &val) == 1) {
- printf ("MCG_CTL:\n");
+ printf("MCG_CTL:\n");
- printf (" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
+ printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
if ((val & (1<<0)) == 1) {
if (read_msr(cpunum, MC_CTL, &val2) == 1) {
- printf (" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf (" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf (" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf (" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf (" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf (" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
}
}
- printf (" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
+ printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
if (((val & (1<<1)) == 2) && (banks>1)) {
if (read_msr(cpunum, MC_CTL+4, &val2) == 1) {
- printf (" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf (" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf (" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf (" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf (" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf (" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
- printf (" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
- printf (" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
- printf (" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
+ printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
+ printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
}
}
- printf (" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
+ printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
if ((val & (1<<2)) == 4 && (banks>2)) {
if (read_msr(cpunum, MC_CTL+8, &val2) == 1) {
- printf (" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf (" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf (" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf (" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf (" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf (" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
}
}
- printf (" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
+ printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
if ((val & (1<<3)) == 8 && (banks>3)) {
if (read_msr(cpunum, MC_CTL+12, &val2) == 1) {
- printf (" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
}
}
}
- printf ("\n");
+ printf("\n");
printf(" 31 23 15 7 \n");
for (i=0; i<banks; i++) {
- printf ("Bank: %u (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
- printf ("MC%uCTL: ", i);
+ printf("Bank: %u (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
+ printf("MC%uCTL: ", i);
dumpmsr_bin (cpunum, MC_CTL+i*4, 32);
- printf ("MC%uSTATUS: ", i);
+ printf("MC%uSTATUS: ", i);
dumpmsr_bin (cpunum, MC_STATUS+i*4, 32);
- printf ("MC%uADDR: ", i);
+ printf("MC%uADDR: ", i);
dumpmsr_bin (cpunum, MC_ADDR+i*4, 32);
- printf ("MC%uMISC: ", i);
+ printf("MC%uMISC: ", i);
dumpmsr_bin (cpunum, MC_MISC+i*4, 32);
- printf ("\n");
+ printf("\n");
}
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/bugs.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: bugs.c,v 1.5 2004/06/02 22:29:29 davej Exp $
- * This file is part of x86info.
* (C) 2002 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -23,7 +21,7 @@
if (tuple(cpu) > 0x681) {
if (read_msr (cpu->number, MSR_CLKCTL, &val) == 1) {
if ((val & 0xfff00000) != 0x20000000) {
- printf ("CLK_CTL is programmed to %08llx, instead of %08llx\n",
+ printf("CLK_CTL is programmed to %08llx, instead of %08llx\n",
val, ((val&~0xfff00000)|0x20000000));
}
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/dumppsb.c
^
|
| @@ -1,3 +1,10 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * PSB decoding routines.
+ */
#include <stdio.h>
#include <unistd.h>
#include <fcntl.h>
@@ -6,8 +13,9 @@
#include <ctype.h>
#include <sys/mman.h>
-#include "powernow.h"
#include "../x86info.h"
+#include "AMD.h"
+#include "powernow.h"
#define START 0x000c0000L
#define END 0x000ffff0L
@@ -41,7 +49,7 @@
unsigned int fid, vid;
fd=open("/dev/mem", O_RDONLY);
- if (fd==-1) {
+ if (fd == -1) {
perror("/dev/mem");
return;
}
@@ -56,58 +64,58 @@
return;
}
- for (i=0;i<ROMSIZE;i++) {
+ for (i=0; i<ROMSIZE; i++) {
if (memcmp(p, "AMDK7PNOW!", 10) == 0){
- printf ("Found PSB header at %p\n", p);
+ printf("Found PSB header at %p\n", p);
psb = (struct psb_s *) p;
- printf ("Table version: 0x%x\n", (unsigned int)psb->tableversion);
+ printf("Table version: 0x%x\n", (unsigned int)psb->tableversion);
if (psb->tableversion != 0x12) {
- printf ("Sorry, only v1.2 tables supported right now\n");
+ printf("Sorry, only v1.2 tables supported right now\n");
goto out;
}
- printf ("Flags: 0x%x ", (unsigned int) psb->flags);
+ printf("Flags: 0x%x ", (unsigned int) psb->flags);
if ((psb->flags & 1)==0) {
- printf ("(Mobile voltage regulator)\n");
+ printf("(Mobile voltage regulator)\n");
} else {
- printf ("(Desktop voltage regulator)\n");
+ printf("(Desktop voltage regulator)\n");
}
- printf ("Settling Time: %d microseconds.\n",
+ printf("Settling Time: %d microseconds.\n",
(int)psb->settlingtime);
- printf ("Has %d PST tables. (Only dumping ones relevant to this CPU).\n",
+ printf("Has %d PST tables. (Only dumping ones relevant to this CPU).\n",
(int)psb->numpst);
p += sizeof (struct psb_s);
pst = (struct pst_s *) p;
- for (i = 0 ; i <psb->numpst; i++) {
+ for (i=0 ; i<psb->numpst; i++) {
pst = (struct pst_s *) p;
numpstates = pst->numpstates;
if ((etuple(cpu) == pst->cpuid) && (maxfid==pst->maxfid) && (startvid==pst->startvid))
{
- printf (" PST:%d (@%p)\n", i, pst);
- printf (" cpuid: 0x%x\t", pst->cpuid);
- printf (" fsb: %d\t", (int)pst->fsbspeed);
- printf (" maxFID: 0x%x\t", (unsigned int)pst->maxfid);
- printf (" startvid: 0x%x\n", (unsigned int)pst->startvid);
- printf (" num of p states in this table: %d\n", numpstates);
+ printf(" PST:%d (@%p)\n", i, pst);
+ printf(" cpuid: 0x%x\t", pst->cpuid);
+ printf(" fsb: %d\t", (int)pst->fsbspeed);
+ printf(" maxFID: 0x%x\t", (unsigned int)pst->maxfid);
+ printf(" startvid: 0x%x\n", (unsigned int)pst->startvid);
+ printf(" num of p states in this table: %d\n", numpstates);
p = (char *) pst + sizeof (struct pst_s);
- for (j=0 ; j < numpstates; j++) {
+ for (j=0 ; j<numpstates; j++) {
fid = *p++;
- printf (" FID: 0x%x (%.1fx [%.0fMHz])\t", fid,
+ printf(" FID: 0x%x (%.1fx [%.0fMHz])\t", fid,
fid_codes[fid], pst->fsbspeed * fid_codes[fid]);
vid = *p++;
- printf ("VID: 0x%x (%0.3fV)\n", vid, mobile_vid_table[vid]);
+ printf("VID: 0x%x (%0.3fV)\n", vid, mobile_vid_table[vid]);
}
- printf ("\n");
+ printf("\n");
} else {
p = (char *) pst + sizeof (struct pst_s);
- for (j=0 ; j < numpstates; j++)
+ for (j=0 ; j<numpstates; j++)
p+=2;
}
}
@@ -117,12 +125,12 @@
}
out:
- if (munmap(p, ROMSIZE)==-1) {
+ if (munmap(p, ROMSIZE) == -1) {
perror("munmap");
exit(EXIT_FAILURE);
}
- if (close(fd)==-1) {
+ if (close(fd) == -1) {
perror("close");
exit(EXIT_FAILURE);
}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/AMD/fam10h.regs
^
|
| @@ -0,0 +1,1473 @@
+# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+#
+# Copyright (C) 2008 Advanced Micro Devices, Inc.
+
+# This file contains information from:
+# - "31116 Rev 3.06 - March 2008, BIOS and Kernel Developer's Guide (BKDG)
+# for AMD Family 10h Processors"
+
+# See scripts/createheader.py for the general format of this register
+# definitions.
+
+{LSMCAaddr=0x0000;load-store MCA address
+ ADDR:48
+ :16
+} # alias of MC3_ADDR
+
+{LSMCAstatus=0x0001;load-store MCE status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :25
+ UECC:1
+ CECC:1
+ SYND:8
+ :2
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+} # alias of MC3_STATUS
+
+{TSC=0x0010;time-stamp counter
+ TSC:64
+}
+
+{APIC_BASE=0x001b;APIC base address
+ :8
+ BSC:1
+ :2
+ ApicEn:1
+ ApicBar:36
+ :16
+}
+
+{EBL_CR_POWERON=0x002a;cluster ID
+ :16
+ ClusterID:2
+ :46
+}
+
+{MTRRcap=0x00fe;MTRR capabilities
+ MtrrCapVCnt:8
+ MtrrCapFix:1
+ :1
+ MtrrCapWc:1
+ :53
+}
+
+{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector
+ SYSENTER_CS:16
+ :48
+}
+
+{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer
+ SYSENTER_ESP:32
+ :32
+}
+
+{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer
+ SYSENTER_EIP:32
+ :32
+}
+
+{MCG_CAP=0x0179;global MC capabilities
+ Count:8
+ MCG_CTL_P:1
+ :55
+}
+
+{MCG_STAT=0x017a;global MC status
+ RIPV:1
+ EIPV:1
+ MCIP:1
+ :61
+}
+
+{MCG_CTL=0x017b;global MC control
+ DCE:1
+ ICE:1
+ BUE:1
+ LSE:1
+ NBE:1
+ FRE:1
+ :58
+}
+
+{DBG_CTL_MSR=0x01d9;debug control
+ LBR:1
+ BTF:1
+ PB0:1
+ PB1:1
+ PB2:1
+ PB3:1
+ :58
+}
+
+{BR_FROM=0x01db;last branch from IP
+ LastBranchFromIP:64
+}
+
+{BR_TO=0x01dc;last branch to IP
+ LastBranchToIP:64
+}
+
+{LastExceptionFromIP=0x01dd;last exception from IP
+ LastIntFromIP:64
+}
+
+{LastExceptionToIP=0x01de;last exception to IP
+ LastIntToIP:64
+}
+
+{MTRRphysBase0=0x0200;base of variable-size MTRR (0)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask0=0x0201;mask of variable-size MTRR (0)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase1=0x0202;base of variable-size MTRR (1)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask1=0x0203;mask of variable-size MTRR (1)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase2=0x0204;base of variable-size MTRR (2)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask2=0x0205;mask of variable-size MTRR (2)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase3=0x0206;base of variable-size MTRR (3)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask3=0x0207;mask of variable-size MTRR (3)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase4=0x0208;base of variable-size MTRR (4)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask4=0x0209;mask of variable-size MTRR (4)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase5=0x020a;base of variable-size MTRR (5)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask5=0x020b;mask of variable-size MTRR (5)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase6=0x020c;base of variable-size MTRR (6)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask6=0x020d;mask of variable-size MTRR (6)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase7=0x020e;base of variable-size MTRR (7)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask7=0x020f;mask of variable-size MTRR (7)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRfix64K_00000=0x0250;fixed range MTRR
+ 0xxxxType:8
+ 1xxxxType:8
+ 2xxxxType:8
+ 3xxxxType:8
+ 4xxxxType:8
+ 5xxxxType:8
+ 6xxxxType:8
+ 7xxxxType:8
+}
+
+{MTRRfix16K_80000=0x0258;fixed range MTRR
+ 80xxxType:8
+ 84xxxType:8
+ 88xxxType:8
+ 8CxxxType:8
+ 90xxxType:8
+ 94xxxType:8
+ 98xxxType:8
+ 9CxxxType:8
+}
+
+{MTRRfix16K_A0000=0x0259;fixed range MTRR
+ A0xxxType:8
+ A4xxxType:8
+ A8xxxType:8
+ ACxxxType:8
+ B0xxxType:8
+ B4xxxType:8
+ B8xxxType:8
+ BCxxxType:8
+}
+
+{MTRRfix4K_C0000=0x0268;fixed range MTRR
+ C0xxxType:8
+ C1xxxType:8
+ C2xxxType:8
+ C3xxxType:8
+ C4xxxType:8
+ C5xxxType:8
+ C6xxxType:8
+ C7xxxType:8
+}
+
+{MTRRfix4K_C8000=0x0269;fixed range MTRR
+ C8xxxType:8
+ C9xxxType:8
+ CAxxxType:8
+ CBxxxType:8
+ CCxxxType:8
+ CDxxxType:8
+ CExxxType:8
+ CFxxxType:8
+}
+
+{MTRRfix4K_D0000=0x026a;fixed range MTRR
+ D0xxxType:8
+ D1xxxType:8
+ D2xxxType:8
+ D3xxxType:8
+ D4xxxType:8
+ D5xxxType:8
+ D6xxxType:8
+ D7xxxType:8
+}
+
+{MTRRfix4K_D8000=0x026b;fixed range MTRR
+ D8xxxType:8
+ D9xxxType:8
+ DAxxxType:8
+ DBxxxType:8
+ DCxxxType:8
+ DDxxxType:8
+ DExxxType:8
+ DFxxxType:8
+}
+
+{MTRRfix4K_E0000=0x026c;fixed range MTRR
+ E0xxxType:8
+ E1xxxType:8
+ E2xxxType:8
+ E3xxxType:8
+ E4xxxType:8
+ E5xxxType:8
+ E6xxxType:8
+ E7xxxType:8
+}
+
+{MTRRfix4K_E8000=0x026d;fixed range MTRR
+ E8xxxType:8
+ E9xxxType:8
+ EAxxxType:8
+ EBxxxType:8
+ ECxxxType:8
+ EDxxxType:8
+ EExxxType:8
+ EFxxxType:8
+}
+
+{MTRRfix4K_F0000=0x026e;fixed range MTRR
+ F0xxxType:8
+ F1xxxType:8
+ F2xxxType:8
+ F3xxxType:8
+ F4xxxType:8
+ F5xxxType:8
+ F6xxxType:8
+ F7xxxType:8
+}
+
+{MTRRfix4K_F8000=0x026f;fixed range MTRR
+ F8xxxType:8
+ F9xxxType:8
+ FAxxxType:8
+ FBxxxType:8
+ FCxxxType:8
+ FDxxxType:8
+ FExxxType:8
+ FFxxxType:8
+}
+
+{PAT=0x0277;page attribute table
+ PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+}
+
+{MTRRdefType=0x02ff;MTRR default memory type
+ MemType:8
+ :2
+ MtrrDefTypeFixEn:1
+ MtrrDefTypeEn:1
+ :52
+}
+
+{MC0_CTL=0x0400;data cache MC control
+ ECCI:1
+ ECCM:1
+ DECC:1
+ DMTP:1
+ DSTP:1
+ L1TP:1
+ L2TP:1
+ :57
+}
+
+{MC0_STATUS=0x0401;data cache MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :4
+ Syndrome:8
+ :8
+ Scrub:1
+ :4
+ UECC:1
+ CECC:1
+ Syndrome:8
+ :2
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC0_ADDR=0x0402;data cache MC address
+ ADDR:48
+ :16
+}
+
+{MC0_MISC=0x0403;data cache MC miscellaneous
+ :64
+}
+
+{MC1_CTL=0x0404;instruction cache MC control
+ ECCI:1
+ ECCM:1
+ IDP:1
+ IMTP:1
+ ISTP:1
+ L1TP:1
+ L2TP:1
+ :2
+ RDDE:1
+ :54
+}
+
+{MC1_STATUS=0x0405;instruction cache MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :25
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC1_ADDR=0x0406;instruction cache MC address
+ ADDR:48
+ :16
+}
+
+{MC1_MISC=0x0407;instruction cache MC miscellaneous
+ :64
+}
+
+{MC2_CTL=0x0408;bus unit MC control
+ SRDE_HP:1
+ SRDE_TLB:1
+ SRDE_ALL:1
+ L2T_PAR:1
+ L2T_CECC:1
+ L2T_UECC:1
+ L2D_PAR:1
+ L2D_CECC:1
+ L2D_UECC:1
+ :1
+ VB_PAR:1
+ PDC_PAR:1
+ :52
+}
+
+{MC2_STATUS=0x0409;bus unit MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :20
+ Scrub:1
+ :4
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC2_ADDR=0x040a;bus unit MC address register
+ ADDR:48
+ :16
+}
+
+{MC2_MISC=0x040b;bus unit MC miscellaneous
+ :64
+}
+
+{MC3_CTL=0x040c;load store unit MC control
+ SRDE_L:1
+ SRDE_S:1
+ :62
+}
+
+{MC3_STATUS=0x040d;load store unit MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :25
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC3_ADDR=0x040e;load store unit MC address
+ ADDR:48
+ :16
+}
+
+{MC3_MISC=0x040f;load store unit MC miscellaneous
+ :64
+}
+
+{MC4_CTL=0x0410;northbridge MC control
+ CECCEn:1
+ UECCEn:1
+ CrcErr0En:1
+ CrcErr1En:1
+ CrcErr2En:1
+ SyncPkt0En:1
+ SyncPkt1En:1
+ SyncPkt2En:1
+ MstrAbrtEn:1
+ TgtAbrtEn:1
+ GartTblWkEn:1
+ AtomicRMWEn:1
+ WDTRptEn:1
+ DevErrEn:1
+ L3ArrayCorEn:1
+ L3ArrayUCEn:1
+ HtProtEn:1
+ HtDataEn:1
+ DramParEn:1
+ RtryHt0En:1
+ RtryHt1En:1
+ RtryHt2En:1
+ RtryHt3En:1
+ CrcErr3En:1
+ SyncPkt3En:1
+ McaUsPwDatErrEn:1
+ NbArrayParEn:1
+ TblWlkDatErrEn:1
+ :36
+}
+
+{MC4_STATUS=0x0411;northbridge MC status
+ ErrorCode:16
+ ErrorCodeExt:5
+ :3
+ Syndrome:8
+ ErrCpu0:1
+ ErrCpu1:1
+ ErrCpu2:1
+ ErrCpu3:1
+ LDTLink0:1
+ LDTLink1:1
+ LDTLink2:1
+ LDTLink3:1
+ Scrub:1
+ SubLink:1
+ McaStatSubCache:2
+ :1
+ UECC:1
+ CECC:1
+ Syndrome:8
+ :2
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ Over:1
+ Val:1
+}
+
+{MC4_ADDR=0x0412;northbridge MC address
+ :1
+ ErrAddr:47
+ :16
+}
+
+{MC4_MISC0=0x0413;northbridge MC misc (thresholding) (0 - DRAM)
+ :24
+ BlkPtr:8
+ ErrCnt:12
+ :4
+ Ovrflw:1
+ IntType:2
+ CntEn:1
+ LvtOffset:4
+ :5
+ Locked:1
+ CntP:1
+ Valid:1
+}
+
+{MC5_CTL=0x0414;fixed issue reorder buffer MC control
+ CPUWDT:1
+ :63
+}
+
+{MC5_STATUS=0x0415;fixed issue reorder buffer MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :4
+ Syndrome:8
+ :8
+ Scrub:1
+ :4
+ UECC:1
+ CECC:1
+ Syndrome:8
+ :2
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC5_ADDR=0x0416;fixed issue reorder buffer MC address
+ ADDR:48
+ :16
+}
+
+{MC5_MISC=0x0417;fixed issue reorder buffer MC miscellaneous
+ State:12
+ :52
+}
+
+{EFER=0xc0000080;extended feature enable
+ SYSCALL:1
+ :7
+ LME:1
+ :1
+ LMA:1
+ NXE:1
+ SVME:1
+ LMSLE:1
+ FFXSE:1
+ :49
+}
+
+{STAR=0xc0000081;SYSCALL target address
+ Target:32
+ SysCallSel:16
+ SysRetSel:16
+}
+
+{STAR64=0xc0000082;long mode SYSCALL target address
+ LSTAR:64
+}
+
+{STARCOMPAT=0xc0000083;compat mode SYSCALL target address
+ CSTAR:64
+}
+
+{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask
+ MASK:32
+ :32
+}
+
+{FS_BASE=0xc0000100;FS base
+ FS_BASE:64
+}
+
+{GS_BASE=0xc0000101;GS base
+ GS_BASE:64
+}
+
+{KernelGSbase=0xc0000102;kernel GS base
+ KernelGSBase:64
+}
+
+{TSC_AUX=0xc0000103;auxiliary time stamp counter data
+ TscAux:32
+ :32
+}
+
+{MC4_MISC1=0xc0000408;northbridge MC misc (thresholding) (1 - link)
+ :24
+ BlkPtr:8
+ ErrCnt:12
+ :4
+ Ovrflw:1
+ IntType:2
+ CntEn:1
+ LvtOffset:4
+ :5
+ Locked:1
+ CntP:1
+ Valid:1
+}
+
+{MC4_MISC2=0xc0000409;northbridge MC misc (thresholding) (2 - L3 cache)
+ :24
+ BlkPtr:8
+ ErrCnt:12
+ :4
+ Ovrflw:1
+ IntType:2
+ CntEn:1
+ LvtOffset:4
+ :5
+ Locked:1
+ CntP:1
+ Valid:1
+}
+
+{MC4_MISC3=0xc000040a;northbridge MC misc (thresholding) (3)
+ :24
+ BlkPtr:8
+ :32
+}
+
+{PERF_CTL0=0xc0010000;performance event select (0)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ :1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :4
+ GuestOnly:1
+ HostOnly:1
+ :22
+}
+
+{PERF_CTL1=0xc0010001;performance event select (1)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ :1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :4
+ GuestOnly:1
+ HostOnly:1
+ :22
+}
+
+{PERF_CTL2=0xc0010002;performance event select (2)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ :1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :4
+ GuestOnly:1
+ HostOnly:1
+ :22
+}
+
+{PERF_CTL3=0xc0010003;performance event select (3)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ :1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :4
+ GuestOnly:1
+ HostOnly:1
+ :22
+}
+
+{PERF_CTR0=0xc0010004;performance event counter (0)
+ CTR:48
+ :16
+}
+
+{PERF_CTR1=0xc0010005;performance event counter (1)
+ CTR:48
+ :16
+}
+
+{PERF_CTR2=0xc0010006;performance event counter (2)
+ CTR:48
+ :16
+}
+
+{PERF_CTR3=0xc0010007;performance event counter (3)
+ CTR:48
+ :16
+}
+
+{SYS_CFG=0xc0010010;system configuration
+ :8
+ SetDirtyEnE:1
+ SetDirtyEnS:1
+ SetDirtyEnO:1
+ :5
+ ChxToDirtyDis:1
+ SysUcLockEn:1
+ MtrrFixDramEn:1
+ MtrrFixDramModeEn:1
+ MtrrVarDramEn:1
+ MtrrTom2En:1
+ Tom2ForceMemTypeWB:1
+ :41
+}
+
+{HWCR=0xc0010015;hardware configuration
+ SmmLock:1
+ SlowFence:1
+ :1
+ TlbCacheDis:1
+ INVD_WBINVD:1
+ :3
+ IgnneEm:1
+ MonMwaitDis:1
+ MonMwaitUserEn:1
+ LimitCpuidStdMaxVal:1
+ HltXSpCycEn:1
+ SmiSpCycDis:1
+ RsmSpCycDis:1
+ SseDis:1
+ :1
+ Wrap32Dis:1
+ McStatusWrEn:1
+ :1
+ IoCfgGpFault:1
+ MisAlignSseDis:1
+ :1
+ ForceUsRdWrSzPrb:1
+ TscFreqSel:1
+ :39
+}
+
+{IORR_BASE0=0xc0010016;base of variable I/O range (0)
+ :3
+ WrMem:1
+ RdMem:1
+ :7
+ PhyBase:36
+ :16
+}
+
+{IORR_MASK0=0xc0010017;mask of variable I/O range (0)
+ :11
+ Valid:1
+ PhyMask:36
+ :16
+}
+
+{IORR_BASE1=0xc0010018;base of variable I/O range (1)
+ :3
+ WrMem:1
+ RdMem:1
+ :7
+ PhyBase:36
+ :16
+}
+
+{IORR_MASK1=0xc0010019;mask of variable I/O range (1)
+ :11
+ Valid:1
+ PhyMask:36
+ :16
+}
+
+{TOP_MEM=0xc001001a;top of memory address
+ :23
+ TOM:25
+ :16
+}
+
+{TOM2=0xc001001d;second top of memory address
+ :23
+ TOM2:25
+ :16
+}
+
+{NB_CFG=0xc001001f;northbridge configuration
+ :9
+ DisRefUseFreeBuf:1
+ DisXdsBypass:1
+ :20
+ DisCohLdtCfg:1
+ :4
+ DisDatMsk:1
+ :8
+ DisUsSysMgtReqToNcHt:1
+ EnableCf8ExtCfg:1
+ :3
+ DisOrderRdRsp:1
+ :3
+ InitApicIdCpuIdLo:1
+ :9
+}
+
+{MCEredirection=0xc0010022;MCE redirection
+ RedirVector:8
+ RedirVecEn:1
+ RedirSmiEn:1
+ :54
+}
+
+{ProcessorNameString0=0xc0010030;processor name string (0)
+ CpuNameString:64
+}
+
+{ProcessorNameString1=0xc0010031;processor name string (1)
+ CpuNameString:64
+}
+
+{ProcessorNameString2=0xc0010032;processor name string (2)
+ CpuNameString:64
+}
+
+{ProcessorNameString3=0xc0010033;processor name string (3)
+ CpuNameString:64
+}
+
+{ProcessorNameString4=0xc0010034;processor name string (4)
+ CpuNameString:64
+}
+
+{ProcessorNameString5=0xc0010035;processor name string (5)
+ CpuNameString:64
+}
+
+{MC0_CTL_MASK=0xc0010044;data cache MC control mask
+ ECCI:1
+ ECCM:1
+ DECC:1
+ DMTP:1
+ DSTP:1
+ L1TP:1
+ L2TP:1
+ :57
+}
+
+{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask
+ ECCI:1
+ ECCM:1
+ IDP:1
+ IMTP:1
+ ISTP:1
+ L1TP:1
+ L2TP:1
+ :2
+ RDDE:1
+ :54
+}
+
+{MC2_CTL_MASK=0xc0010046;bus unit MC control mask
+ SRDE_HP:1
+ SRDE_TLB:1
+ SRDE_ALL:1
+ L2T_PAR:1
+ L2T_CECC:1
+ L2T_UECC:1
+ L2D_PAR:1
+ L2D_CECC:1
+ L2D_UECC:1
+ :1
+ VB_PAR:1
+ PDC_PAR:1
+ :52
+}
+
+{MC3_CTL_MASK=0xc0010047;load store unit MC control mask
+ SRDE_L:1
+ SRDE_S:1
+ :62
+}
+
+{MC4_CTL_MASK=0xc0010048;northbridge MC control mask
+ CECCEn:1
+ UECCEn:1
+ CrcErr0En:1
+ CrcErr1En:1
+ CrcErr2En:1
+ SyncPkt0En:1
+ SyncPkt1En:1
+ SyncPkt2En:1
+ MstrAbrtEn:1
+ TgtAbrtEn:1
+ GartTblWkEn:1
+ AtomicRMWEn:1
+ WDTRptEn:1
+ DevErrEn:1
+ L3ArrayCorEn:1
+ L3ArrayUCEn:1
+ HtProtEn:1
+ HtDataEn:1
+ DramParEn:1
+ RtryHt0En:1
+ RtryHt1En:1
+ RtryHt2En:1
+ RtryHt3En:1
+ CrcErr3En:1
+ SyncPkt3En:1
+ McaUsPwDatErrEn:1
+ NbArrayParEn:1
+ TblWlkDatErrEn:1
+ :36
+}
+
+{MC5_CTL_MASK=0xc0010049;fixed issue reorder buffer MC control mask
+ CPUWDT:1
+ :63
+}
+
+{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control
+ :1
+ SmiEn_0:1
+ :1
+ SmiEn_1:1
+ :1
+ SmiEn_2:1
+ :1
+ SmiEn_3:1
+ :7
+ IoTrapEn:1
+ :48
+}
+
+{IntPendingMessage=0xc0010055;interrupt pending and CMP-halt
+ IOMsgAddr:16
+ IOMsgData:8
+ IntrPndMsgDis:1
+ IntrPndMsg:1
+ IORd:1
+ SmiOnCmpHalt:1
+ :36
+}
+
+{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle
+ IoPortAddress:16
+ IoData:8
+ :1
+ IoCycleEn:1
+ IoRd:1
+ :37
+}
+
+{MmioConfigBase=0xc0010058;MMIO configuration base address
+ Enable:1
+ TrapAccess:1
+ SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256
+ :14
+ MmiocCfgBaseAddr:28
+ :16
+}
+
+{PstateCurrentLimit=0xc0010061;P-state current limit
+ CurPstateLimit:3
+ :1
+ PstateMaxVal:3
+ :57
+}
+
+{PstateControl=0xc0010062;P-state control
+ PstateCmd:3
+ :61
+}
+
+{PstateStatus=0xc0010063;P-state status
+ CurPstate:3
+ :61
+}
+
+{Pstate0=0xc0010064;P-state 0
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :6
+ NbDid:1
+ :2
+ NbVid:7
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate1=0xc0010065;P-state 1
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :6
+ NbDid:1
+ :2
+ NbVid:7
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate2=0xc0010066;P-state 2
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :6
+ NbDid:1
+ :2
+ NbVid:7
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate3=0xc0010067;P-state 3
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :6
+ NbDid:1
+ :2
+ NbVid:7
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate4=0xc0010068;P-state 4
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :6
+ NbDid:1
+ :2
+ NbVid:7
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{COFVIDcontrol=0xc0010070;COFVID control
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ PstateId:3
+ :3
+ NbDid:1
+ :2
+ NbVid:7
+ :32
+}
+
+{COFVIDstatus=0xc0010071;COFVID status
+ CurCpuFid:6
+ CurCpuDid:3
+ CurCpuVid:7
+ CurPstate:3
+ :3
+ CurNbDid:1
+ :2
+ CurNbVid:7
+ StartupPstate:3
+ MaxVid:7
+ MinVid:7
+ MaxCpuCof:6
+ :1
+ CurPstateLimit:3
+ MaxNbFid:5
+}
+
+{CpuWdTmrCfg=0xc0010074;CPU watchdog timer
+ CpuWdtEn:1
+ CpuWdtTimeBase:2
+ CpuWdtCountSel:4
+ :57
+}
+
+{SMM_BASE=0xc0010111;SMM base address
+ SMM_BASE:32
+ :32
+}
+
+{SMMAddr=0xc0010112;SMM TSeg base address
+ :17
+ TSegBase:31
+ :16
+}
+
+{SMMMask=0xc0010113;SMM Tseg mask
+ AValid:1
+ TValid:1
+ AClose:1
+ TClose:1
+ AMTypeIoWc:1
+ TMTypeIoWc:1
+ :2
+ AMTypeDram:3
+ :1
+ TMTypeDram:3
+ :2
+ TSegMask:31
+ :16
+}
+
+{VM_CR=0xc0010114;virtual machine control
+ dpd:1
+ r_init:1
+ dis_a20m:1
+ Lock:1
+ Svme_Disable:1
+ :59
+}
+
+{IGNNE=0xc0010115;IGNNE
+ IGNNE:1
+ :63
+}
+
+# {SMM_CTL=0xc0010116;SMM control
+# smm_dismiss:1
+# smm_enter:1
+# smi_cyle:1
+# smm_exit:1
+# rsm_cycle:1
+# :59
+# } # write-only
+
+{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address
+ VM_HSAVE_PA:64
+}
+
+# {SMM_CTL=0xc0010118;SVM lock key
+# SvmLockKey:64
+# } # write-only
+
+{SMIstatus=0xc001011a;local SMI status
+ IoTrapSts:4
+ :4
+ MceRedirSts:1
+ SmiOnCmpHaltSts:1
+ IntPendSmiSts:1
+ :5
+ SmiSrcLvtLcy:1
+ SmiSrcLvtExt:1
+ SmiSrcThrCntDram:1
+ SmiSrcThrCntHt:1
+ SmiSrcThrCntL3:1
+ :1
+ SmiSrcOnLineSpare:1
+ :41
+}
+
+{OSVW_ID_Length=0xc0010140;OS visible work-around
+ OSVW_ID_Length:16
+ :48
+}
+
+{OsvwStatus=0xc0010141;OS visible work-around status bits
+ OsvwStatusBits:64
+}
+
+{CPUIDFeatures=0xc0011004;CPUID features
+ Features:32
+ Features:32
+}
+
+{CPUIDExtFeatures=0xc0011005;extended CPUID features
+ ExtFeaturesEcx:32
+ ExtFeaturesEdx:32
+}
+
+{DC_CFG=0xc0011022;data cache configuration
+ :34
+ REQ_CTR:2
+ :28
+}
+
+{BU_CFG=0xc0011023;bus unit configuration
+ :48
+ WbEnhWsbDis:1
+ :15
+}
+
+{BU_CFG2=0xc001102A;bus unit configuration 2
+ :2
+ FrcWTMemTypToWPDis:1
+ :12
+ CILinesToNbDis:1
+ :13
+ Smash1GPages:1
+ :34
+}
+
+{IbsFetchCtl=0xc0011030;IBS fetch control
+ IbsFetchMaxCnt:16
+ IbsFetchCnt:16
+ IbsFetchLat:16
+ IbsFetchEn:1
+ IbsFetchVal:1
+ IbsFetchComp:1
+ IbsIcMiss:1
+ IbsPhyAddrValid:1
+ IbsL1TlbPgSz:2
+ IbsL1TlbMiss:1
+ IbsL2TlbMiss:1
+ IbsRandEn:1
+ :6
+}
+
+{IbsFetchLinAd=0xc0011031;IBS fetch linear address
+ IbsFetchLinAd:64
+}
+
+{IbsFetchPhysAd=0xc0011032;IBS fetch physical address
+ IbsFetchPhysAd:64
+}
+
+{IbsOpCtl=0xc0011033;IBS execution control
+ IbsOpMaxCnt:16
+ :1
+ IbsOpEn:1
+ IbsOpVal:1
+ :45
+}
+
+{IbsOpRip=0xc0011034;IBS Op logical address
+ IbsOpRip:64
+}
+
+{IbsOpData=0xc0011035;IBS Op data
+ IbsCompToRetCtr:16
+ IbsTagToRetCtr:16
+ IbsOpBrnResync:1
+ IbsOpMispReturn:1
+ IbsOpReturn:1
+ IbsOpBrnTaken:1
+ IbsOpBrnMisp:1
+ IbsOpBrnRet:1
+ :26
+}
+
+{IbsOpData2=0xc0011036;IBS Op data 2
+ NbIbsReqSrc:3
+ :1
+ NbIbsReqDstProc:1
+ NbIbsReqCacheHitSt:1
+ :58
+}
+
+{IbsOpData3=0xc0011037;IBS Op data 3
+ IbsLdOp:1
+ IbsStOp:1
+ IbsDcL1tlbMiss:1
+ IbsDcL2tlbMiss:1
+ IbsDcL1tlbHit2M:1
+ IbsDcL1tlbHit1G:1
+ IbsDcL2tlbHit2M:1
+ IbsDcMiss:1
+ IbsDcMisAcc:1
+ IbsDcLdBnkCon:1
+ IbsDcStBnkCon:1
+ IbsDcStToLdFwd:1
+ IbsDcStToLdCan:1
+ IbsDcUcMemAcc:1
+ IbsDcWcMemAcc:1
+ IbsDcLockedOp:1
+ IbsDcMabHit:1
+ IbsDcLinAddrValid:1
+ IbsDcPhyAddrValid:1
+ :13
+ IbsDcMissLat:16
+ :16
+}
+
+{IbsDcLinAd=0xc0011038;IBS DC linear address
+ IbsDcLinAd:64
+}
+
+{IbsDcPhysAd=0xc0011039;IBS DC physical address
+ IbsDcPhysAd:64
+}
+
+{IbsControl=0xc001103a;IBS control
+ LvtOffset:4
+ :4
+ LvtOffsetVal:1
+ :55
+}
+
+### Local Variables: ###
+### mode:shell-script ###
+### End: ###
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/identify.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: identify.c,v 1.54 2004/06/11 12:35:05 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
@@ -9,8 +7,6 @@
* Licensed under the terms of the GNU GPL License version 2.
*
* AMD-specific information
- *
- * http://www.pbase.com/image/17079307/original
*/
#include <stdio.h>
@@ -35,7 +31,7 @@
s[0] = 0;
cont = 0;
- for (i=0; (r!=NULL) && (i<ARRAY_SIZE(k8_names)); i++) {
+ for (i=0; (r != NULL) && (i<ARRAY_SIZE(k8_names)); i++) {
p = NULL;
id = 1<<i;
if (r->nameid & id)
@@ -54,7 +50,7 @@
snprintf(c->name, CPU_NAME_LEN, "Unknown CPU");
}
-void set_k8_revinfo(int id, struct cpudata *c)
+static void set_k8_revinfo(int id, struct cpudata *c)
{
int i;
struct k8_rev *r;
@@ -72,19 +68,27 @@
c->connector = r ? r->socketid : 0;
}
-void set_fam10h_revinfo(int id, struct cpudata *c)
+
+static void set_fam10h_name(struct fam10h_rev *r, struct cpudata *c)
{
- unsigned long eax, ebx, ecx, edx;
- int pkg_id;
- const char *p;
-
+ if (!r) {
+ snprintf(c->name, CPU_NAME_LEN, "Unknown CPU");
+ return;
+ }
- p = get_fam10h_revision_name(id);
- if (p)
+ if (r->nameid & _PHENOM)
snprintf(c->name, CPU_NAME_LEN,
- "Quad-Core/Dual-Core/Embedded Opteron (%s)", p);
- else
- snprintf(c->name, CPU_NAME_LEN, "Unknown CPU");
+ "Quad-Core Opteron/Phenom (%s)",
+ r->rev);
+ else if (r->nameid)
+ snprintf(c->name, CPU_NAME_LEN,
+ "Quad-Core Opteron (%s)", r->rev);
+}
+
+static void set_connector(struct cpudata *c)
+{
+ unsigned int eax, ebx, ecx, edx;
+ int pkg_id;
cpuid(c->number, 0x80000001, &eax, &ebx, &ecx, &edx);
pkg_id = (ebx >> 28) & 0xf;
@@ -96,11 +100,43 @@
case 1:
c->connector = CONN_SOCKET_AM2_R2;
break;
+ case 2:
+ c->connector = CONN_SOCKET_S1G2;
+ break;
default:
c->connector = 0;
}
}
+static void set_fam10h_revinfo(int id, struct cpudata *c)
+{
+ int i;
+ struct fam10h_rev *r = NULL;
+
+ for (i=0; i<ARRAY_SIZE(fam10h_revisions); i++) {
+ if (fam10h_revisions[i].eax == id) {
+ r = &fam10h_revisions[i];
+ break;
+ }
+ }
+ set_fam10h_name(r, c);
+ set_connector(c);
+}
+
+static void set_fam11h_revinfo(int id, struct cpudata *c)
+{
+ const char *p;
+
+ p = get_fam11h_revision_name(id);
+ if(p)
+ snprintf(c->name, CPU_NAME_LEN,
+ "AMD Turion X2 Ultra Dual-Core (%s)", p);
+ else
+ snprintf(c->name, CPU_NAME_LEN, "Unknown CPU");
+
+ set_connector(c);
+}
+
static void do_assoc(unsigned long assoc)
{
switch (assoc & 0xff) {
@@ -167,9 +203,9 @@
printf("%lu-way associative. ", a);
}
-static void decode_AMD_cacheinfo(struct cpudata *cpu)
+void decode_AMD_cacheinfo(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
if ((cpu->eflags_edx & 1<<26) && cpu->maxei >= 0x80000019) {
/* 1GB page TLB info */
@@ -177,10 +213,10 @@
printf("L1 Data TLB (1G): ");
do_l2assoc(eax >> 28);
- printf("%lu entries.\n", (eax >> 16) & 0xfff);
+ printf("%u entries.\n", (eax >> 16) & 0xfff);
printf("L1 Instruction TLB (1G): ");
do_l2assoc((eax >> 12) & 0xf);
- printf("%lu entries.\n", eax & 0xfff);
+ printf("%u entries.\n", eax & 0xfff);
}
if (cpu->maxei >= 0x80000005) {
@@ -189,31 +225,31 @@
printf("L1 Data TLB (2M/4M): ");
do_assoc(eax >> 24);
- printf("%lu entries.\n", (eax >> 16) & 0xff);
+ printf("%u entries.\n", (eax >> 16) & 0xff);
printf("L1 Instruction TLB (2M/4M): ");
do_assoc((eax >> 8) & 0xff);
- printf("%lu entries.\n", eax & 0xff);
+ printf("%u entries.\n", eax & 0xff);
printf("L1 Data TLB (4K): ");
do_assoc(ebx >> 24);
- printf("%lu entries.\n", (ebx >> 16) & 0xff);
+ printf("%u entries.\n", (ebx >> 16) & 0xff);
printf("L1 Instruction TLB (4K): ");
do_assoc((ebx >> 8) & 0xff);
- printf("%lu entries.\n", ebx & 0xff);
+ printf("%u entries.\n", ebx & 0xff);
printf("L1 Data cache:\n\t");
- printf("Size: %luKb\t", ecx >> 24);
+ printf("Size: %uKb\t", ecx >> 24);
do_assoc((ecx >> 16) & 0xff);
printf("\n\t");
- printf("lines per tag=%lu\t", (ecx >> 8) & 0xff);
- printf("line size=%lu bytes.\n", ecx & 0xff);
+ printf("lines per tag=%u\t", (ecx >> 8) & 0xff);
+ printf("line size=%u bytes.\n", ecx & 0xff);
printf("L1 Instruction cache:\n\t");
- printf("Size: %luKb\t", edx >> 24);
+ printf("Size: %uKb\t", edx >> 24);
do_assoc((edx >> 16) & 0xff);
printf("\n\t");
- printf("lines per tag=%lu\t", (edx >> 8) & 0xff);
- printf("line size=%lu bytes.\n", edx & 0xff);
+ printf("lines per tag=%u\t", (edx >> 8) & 0xff);
+ printf("line size=%u bytes.\n", edx & 0xff);
}
if ((cpu->eflags_edx & 1<<26) && cpu->maxei >= 0x80000019) {
@@ -222,10 +258,10 @@
printf("L2 Data TLB (1G): ");
do_l2assoc(ebx >> 28);
- printf("%lu entries.\n", (ebx >> 16) & 0xfff);
+ printf("%u entries.\n", (ebx >> 16) & 0xfff);
printf("L2 Instruction TLB (1G): ");
do_l2assoc((ebx >> 12) & 0xf);
- printf("%lu entries.\n", ebx & 0xfff);
+ printf("%u entries.\n", ebx & 0xfff);
}
if (cpu->maxei >= 0x80000006) {
@@ -234,33 +270,33 @@
printf("L2 Data TLB (2M/4M): ");
do_l2assoc(eax >> 28);
- printf("%lu entries.\n", (eax >> 16) & 0xfff);
+ printf("%u entries.\n", (eax >> 16) & 0xfff);
printf("L2 Instruction TLB (2M/4M): ");
do_l2assoc((eax >> 12) & 0xf);
- printf("%lu entries.\n", eax & 0xfff);
+ printf("%u entries.\n", eax & 0xfff);
printf("L2 Data TLB (4K): ");
do_l2assoc(ebx >> 28);
- printf("%lu entries.\n", (ebx >> 16) & 0xfff);
+ printf("%u entries.\n", (ebx >> 16) & 0xfff);
printf("L2 Instruction TLB (4K): ");
do_l2assoc((ebx >> 12) & 0xf);
- printf("%lu entries.\n", ebx & 0xfff);
+ printf("%u entries.\n", ebx & 0xfff);
printf("L2 cache:\n\t");
- printf("Size: %luKb\t", ecx >> 16);
+ printf("Size: %uKb\t", ecx >> 16);
do_l2assoc((ecx >> 12) & 0x0f);
printf("\n\t");
- printf("lines per tag=%lu\t", (ecx >> 8) & 0x0f);
- printf("line size=%lu bytes.\n", ecx & 0xff);
+ printf("lines per tag=%u\t", (ecx >> 8) & 0x0f);
+ printf("line size=%u bytes.\n", ecx & 0xff);
if (family(cpu) == 0x10) {
/* family 0x10 has shared L3 cache */
printf("L3 (shared) cache:\n\t");
- printf("Size: %luKb\t",
+ printf("Size: %uKb\t",
(edx >> 18) * 512);
do_l2assoc((edx >> 12) & 0x0f);
printf("\n\t");
- printf("lines per tag=%lu\t", (edx >> 8) & 0x0f);
- printf("line size=%lu bytes.\n", edx & 0xff);
+ printf("lines per tag=%u\t", (edx >> 8) & 0x0f);
+ printf("line size=%u bytes.\n", edx & 0xff);
}
}
@@ -274,7 +310,7 @@
*/
static int getL2size(int cpunum)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
cpuid(cpunum, 0x80000006, &eax, &ebx, &ecx, &edx);
return (ecx >> 16);
}
@@ -282,7 +318,7 @@
static int is_mobile(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
if (cpu->maxei >= 0x80000007) {
cpuid(cpu->number, 0x80000007, &eax, &ebx, &ecx, &edx);
if ((edx & (1<<1|1<<2)) == 0)
@@ -297,7 +333,7 @@
static void determine_xp_mp(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
/* There are no mobile MPs. */
if (is_mobile(cpu)) {
@@ -316,19 +352,15 @@
void Identify_AMD(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
amd_nameptr = cpu->name;
- cpu->vendor = VENDOR_AMD;
if (cpu->maxi < 1)
return;
- cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
if (cpu->family == 0xf) {
+ cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
cpu->emodel = (eax >> 16) & 0xf;
cpu->efamily= (eax >> 20) & 0xff;
} else {
@@ -342,6 +374,9 @@
} else if (family(cpu) == 0x10) {
set_fam10h_revinfo(eax, cpu);
return;
+ } else if (family(cpu) == 0x11) {
+ set_fam11h_revinfo(eax, cpu);
+ return;
}
switch (cpu->family) {
@@ -349,7 +384,7 @@
cpu->connector = CONN_SOCKET_3;
break;
}
-
+
switch (tuple(cpu) & 0xff0) {
case 0x430:
add_to_cpuname("Am486DX2-WT");
@@ -669,14 +704,7 @@
void display_AMD_info(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
-
- printf("Family: %u Model: %u Stepping: %u\n",
- family(cpu), model(cpu), cpu->stepping);
- printf ("CPU Model : %s\n", cpu->name);
- get_model_name(cpu);
-
- decode_feature_flags(cpu);
+ unsigned int eax, ebx, ecx, edx;
if (show_msr) {
if (cpu->family == 5)
@@ -688,9 +716,6 @@
if (show_bluesmoke)
decode_athlon_bluesmoke(cpu->number);
- if (show_cacheinfo)
- decode_AMD_cacheinfo(cpu);
-
if (show_pm)
decode_powernow(cpu);
@@ -738,7 +763,5 @@
printf("The physical package has %d of %d "
"possible cores implemented.\n", n, p);
}
-
-
}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/AMD/k8.regs
^
|
| @@ -0,0 +1,1116 @@
+# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+#
+# Copyright (C) 2008 Advanced Micro Devices, Inc.
+
+# This file contains information from:
+# - "26094 Rev 3.30 - February 2006, BIOS and Kernel Developer's Guide
+# for AMD Athlon 64 and AMD Opteron Processors"
+#
+# - "32559 Rev 3.08 - July 2007, BIOS and Kernel Developer's Guide
+# for AMD NPT Family 0Fh Processors"
+#
+# - "24593 Rev 3.14 - September 2007, AMD64 Technology - AMD64
+# Architecture Programmer's Manual Volume 2: System Programming"
+
+
+# See scripts/createheader.py for the general format of this register
+# definitions.
+
+# Todos:
+# - distinguish between NPT and pre-NPT K8 registers
+
+{TSC=0x0010;time-stamp counter
+ PCLKS:64
+}
+
+{APIC_BASE=0x001b;APIC base address
+ :8
+ BSP:1
+ :2
+ ApicEn:1
+ ApicBase:28
+ :24
+}
+
+{EBL_CR_POWERON=0x002a;APIC cluster ID
+ :16
+ ApicClusterID:2
+ :46
+}
+
+{MTRRcap=0x00fe;MTRR capabilities
+ MtrrCapVCnt:8
+ MtrrCapFix:1
+ :1
+ MtrrCapWc:1
+ :53
+}
+
+{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector
+ SYSENTER_CS:16
+ :48
+}
+
+{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer
+ SYSENTER_ESP:32
+ :32
+}
+
+{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer
+ SYSENTER_EIP:32
+ :32
+}
+
+{MCG_CAP=0x0179;global MC capabilities
+ Count:8
+ MCG_CTL_P:1
+ :55
+}
+
+{MCG_STATUS=0x017a;global MC status
+ RIPV:1
+ EIPV:1
+ MCIP:1
+ :61
+}
+
+{MCG_CTL=0x017b;global MC control
+ DCE:1
+ ICE:1
+ BUE:1
+ LSE:1
+ NBE:1
+ :59
+}
+
+{DebugCtl=0x01d9;debug control
+ LBR:1
+ BTF:1
+ PB0:1
+ PB1:1
+ PB2:1
+ PB3:1
+ :58
+}
+
+{LastBranchFromIP=0x01db;last branch from IP
+ LastBranchFromIP:64
+}
+
+{LastBranchToIP=0x01dc;last branch to IP
+ LastBranchToIP:64
+}
+
+{LastExceptionFromIP=0x01dd;last exception from IP
+ LastExceptionFromIP:64
+}
+
+{LastExceptionToIP=0x01de;last exception to IP
+ LastExceptionToIP:64
+}
+
+{MTRRphysBase0=0x0200;base of variable-size MTRR (0)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask0=0x0201;mask of variable-size MTRR (0)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase1=0x0202;base of variable-size MTRR (1)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask1=0x0203;mask of variable-size MTRR (1)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase2=0x0204;base of variable-size MTRR (2)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask2=0x0205;mask of variable-size MTRR (2)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase3=0x0206;base of variable-size MTRR (3)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask3=0x0207;mask of variable-size MTRR (3)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase4=0x0208;base of variable-size MTRR (4)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask4=0x0209;mask of variable-size MTRR (4)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase5=0x020a;base of variable-size MTRR (5)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask5=0x020b;mask of variable-size MTRR (5)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase6=0x020c;base of variable-size MTRR (6)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask6=0x020d;mask of variable-size MTRR (6)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRphysBase7=0x020e;base of variable-size MTRR (7)
+ Type:8
+ :4
+ PhyBase:28
+ :24
+}
+
+{MTRRphysMask7=0x020f;mask of variable-size MTRR (7)
+ :11
+ Valid:1
+ PhysMask:28
+ :24
+}
+
+{MTRRfix64K_00000=0x0250;fixed range MTRR
+ 0xxxxType:8
+ 1xxxxType:8
+ 2xxxxType:8
+ 3xxxxType:8
+ 4xxxxType:8
+ 5xxxxType:8
+ 6xxxxType:8
+ 7xxxxType:8
+}
+
+{MTRRfix16K_80000=0x0258;fixed range MTRR
+ 80xxxType:8
+ 84xxxType:8
+ 88xxxType:8
+ 8CxxxType:8
+ 90xxxType:8
+ 94xxxType:8
+ 98xxxType:8
+ 9CxxxType:8
+}
+
+{MTRRfix16K_A0000=0x0259;fixed range MTRR
+ A0xxxType:8
+ A4xxxType:8
+ A8xxxType:8
+ ACxxxType:8
+ B0xxxType:8
+ B4xxxType:8
+ B8xxxType:8
+ BCxxxType:8
+}
+
+{MTRRfix4K_C0000=0x0268;fixed range MTRR
+ C0xxxType:8
+ C1xxxType:8
+ C2xxxType:8
+ C3xxxType:8
+ C4xxxType:8
+ C5xxxType:8
+ C6xxxType:8
+ C7xxxType:8
+}
+
+{MTRRfix4K_C8000=0x0269;fixed range MTRR
+ C8xxxType:8
+ C9xxxType:8
+ CAxxxType:8
+ CBxxxType:8
+ CCxxxType:8
+ CDxxxType:8
+ CExxxType:8
+ CFxxxType:8
+}
+
+{MTRRfix4K_D0000=0x026a;fixed range MTRR
+ D0xxxType:8
+ D1xxxType:8
+ D2xxxType:8
+ D3xxxType:8
+ D4xxxType:8
+ D5xxxType:8
+ D6xxxType:8
+ D7xxxType:8
+}
+
+{MTRRfix4K_D8000=0x026b;fixed range MTRR
+ D8xxxType:8
+ D9xxxType:8
+ DAxxxType:8
+ DBxxxType:8
+ DCxxxType:8
+ DDxxxType:8
+ DExxxType:8
+ DFxxxType:8
+}
+
+{MTRRfix4K_E0000=0x026c;fixed range MTRR
+ E0xxxType:8
+ E1xxxType:8
+ E2xxxType:8
+ E3xxxType:8
+ E4xxxType:8
+ E5xxxType:8
+ E6xxxType:8
+ E7xxxType:8
+}
+
+{MTRRfix4K_E8000=0x026d;fixed range MTRR
+ E8xxxType:8
+ E9xxxType:8
+ EAxxxType:8
+ EBxxxType:8
+ ECxxxType:8
+ EDxxxType:8
+ EExxxType:8
+ EFxxxType:8
+}
+
+{MTRRfix4K_F0000=0x026e;fixed range MTRR
+ F0xxxType:8
+ F1xxxType:8
+ F2xxxType:8
+ F3xxxType:8
+ F4xxxType:8
+ F5xxxType:8
+ F6xxxType:8
+ F7xxxType:8
+}
+
+{MTRRfix4K_F8000=0x026f;fixed range MTRR
+ F8xxxType:8
+ F9xxxType:8
+ FAxxxType:8
+ FBxxxType:8
+ FCxxxType:8
+ FDxxxType:8
+ FExxxType:8
+ FFxxxType:8
+}
+
+{PAT=0x0277;page attribute table
+ PA0:3
+ :5
+ PA1:3
+ :5
+ PA2:3
+ :5
+ PA3:3
+ :5
+ PA4:3
+ :5
+ PA5:3
+ :5
+ PA6:3
+ :5
+ PA7:3
+ :5
+}
+
+{MTRRdefType=0x02ff;MTRR default memory type
+ MtrrDefMemType:8
+ :2
+ MtrrDefTypeFixEn:1
+ MtrrDefTypeEn:1
+ :52
+}
+
+{MC0_CTL=0x0400;data cache MC control
+ ECCI:1
+ ECCM:1
+ DECC:1
+ DMTP:1
+ DSTP:1
+ L1TP:1
+ L2TP:1
+ :57
+}
+
+{MC0_STATUS=0x0401;data cache MC status
+ ERR_CODE:16
+ EXT_ERR_CODE:4
+ :20
+ SCRUB:1
+ :4
+ UECC:1
+ CECC:1
+ SYND:8
+ :2
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC0_ADDR=0x0402;data cache MC address
+ ADDR:48
+ :16
+}
+
+{MC0_MISC=0x0403;data cache MC miscellaneous
+ :64
+} # K8 NPT only
+
+{MC1_CTL=0x0404;instruction cache MC control
+ ECCI:1
+ ECCM:1
+ IDP:1
+ IMTP:1
+ ISTP:1
+ L1TP:1
+ L2TP:1
+ :2
+ RDDE:1
+ :54
+}
+
+{MC1_STATUS=0x0405;instruction cache MC status
+ ERR_CODE:16
+ EXT_ERR_CODE:4
+ :20
+ SCRUB:1
+ :4
+ UECC:1
+ CECC:1
+ SYND:8
+ :2
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC1_ADDR=0x0406;instruction cache MC address
+ ADDR:48
+ :16
+}
+
+{MC1_MISC=0x0407;instruction cache MC miscellaneous
+ :64
+} # K8 NPT only
+
+{MC2_CTL=0x0408;bus unit MC control
+ S_RDE_HP:1
+ S_RDE_TLB:1
+ S_RDE_ALL:1
+ S_ECC1_TLB:1
+ S_ECC1_HP:1
+ S_ECCM_TLB:1
+ S_ECCM_HP:1
+ L2T_PAR_ICDC:1
+ L2T_PAR_TLB:1
+ L2_PAR_SNP:1
+ L2_PAR_CPB:1
+ L2_PAR_SCR:1
+ L2D_ECC1_TLB:1
+ L2D_ECC1_SNP:1
+ L2D_ECC1_CPB:1
+ L2D_ECCM_TLB:1
+ L2D_ECCM_SNP:1
+ L2D_ECCM_CPB:1
+ L2T_ECC1_SCR:1
+ L2T_ECCM_SCR:1
+ :44
+}
+
+{MC2_STATUS=0x0409;bus unit MC status
+ ERR_CODE:16
+ EXT_ERR_CODE:4
+ :20
+ SCRUB:1
+ :4
+ UECC:1
+ CECC:1
+ SYND:8
+ :2
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC2_ADDR=0x040a;bus unit MC address
+ ADDR:48
+ :16
+}
+
+{MC2_MISC=0x040b;bus unit MC miscellaneous
+ :64
+} # K8 NPT only
+
+{MC3_CTL=0x040c;load store unit MC control
+ S_RDE_L:1
+ S_RDE_S:1
+ :62
+}
+
+{MC3_STATUS=0x040d;load store unit MC status
+ ERR_CODE:16
+ EXT_ERR_CODE:4
+ :20
+ SCRUB:1
+ :4
+ UECC:1
+ CECC:1
+ SYND:8
+ :2
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC3_ADDR=0x040e;load store unit MC address
+ ADDR:48
+ :16
+}
+
+{MC3_MISC=0x040f;load store unit MC miscellaneous
+ :64
+} # K8 NPT only
+
+{MC4_CTL=0x0410;northbridge MC control
+ CorrEccEn:1
+ UnCorrEccEn:1
+ CrcErr0En:1
+ CrcErr1En:1
+ CrcErr2En:1
+ SyncPkt0En:1
+ SyncPkt1En:1
+ SyncPkt2En:1
+ MstrAbrtEn:1
+ TgtAbrtEn:1
+ GartTblWkEn:1
+ AtomicRMWEn:1
+ WchDogTmrEn:1
+ :5
+ DramParEn:1;;K8 NPT
+ :45
+}
+
+{MC4_STATUS=0x0411;northbridge MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :4
+ Syndrome:8
+ ErrCpu0:1
+ ErrCpu1:1
+ :2
+ LDTLink:3
+ :1
+ ErrScrub:1
+ DramChannel:1;;K8 NPT
+ :3
+ UnCorrECC:1
+ CorrECC:1
+ ECC_Synd:8
+ :2
+ PCC:1
+ ErrAddrVal:1
+ ErrMiscVal:1
+ ErrEn:1
+ ErrUnCorr:1
+ ErrOver:1
+ ErrValid:1
+}
+
+{MC4_ADDR=0x0412;northbridge MC address
+ :3
+ ADDR:37
+ :24
+}
+
+{MC4_MISC=0x0413;DRAM errors threshold
+ :32
+ ErrCount:12
+ :4
+ Ovrflw:1
+ IntType:2
+ CntEn:1
+ LvtOff:4
+ :5
+ Locked:1
+ CtrP:1
+ Val:1
+} # K8 NPT only
+
+{EFER=0xc0000080;extended feature enable
+ SYSCALL:1
+ :7
+ LME:1
+ :1
+ LMA:1
+ NXE:1
+ SVME:1;;K8 NPT
+ LMSLE:1
+ FFXSR:1
+ :49
+}
+
+{STAR=0xc0000081;SYSCALL target address
+ Target:32
+ SysCallSel:16
+ SysRetSel:16
+}
+
+{LSTAR=0xc0000082;long mode SYSCALL target address
+ LSTAR:64
+}
+
+{CSTAR=0xc0000083;compat mode SYSCALL target address
+ CSTAR:64
+}
+
+{SF_MASK=0xc0000084;SYSCALL flag mask
+ MASK:32
+ :32
+}
+
+{FSBase=0xc0000100;FS base
+ FS_BASE:64
+}
+
+{GSBase=0xc0000101;GS base
+ GS_BASE:64
+}
+
+{KernelGSbase=0xc0000102;kernel GS base
+ KernelGSBase:64
+}
+
+{PerfEvtSel0=0xc0010000;performance event-select (0)
+ EVENT_MASK:8
+ UNIT_MASK:8
+ USR:1
+ OS:1
+ E:1
+ PC:1
+ INT:1
+ :1
+ EN:1
+ INV:1
+ CNT_MASK:8
+ :32
+}
+
+{PerfEvtSel1=0xc0010001;performance event-select (1)
+ EVENT_MASK:8
+ UNIT_MASK:8
+ USR:1
+ OS:1
+ E:1
+ PC:1
+ INT:1
+ :1
+ EN:1
+ INV:1
+ CNT_MASK:8
+ :32
+}
+
+{PerfEvtSel2=0xc0010002;performance event-select (2)
+ EVENT_MASK:8
+ UNIT_MASK:8
+ USR:1
+ OS:1
+ E:1
+ PC:1
+ INT:1
+ :1
+ EN:1
+ INV:1
+ CNT_MASK:8
+ :32
+}
+
+{PerfEvtSel3=0xc0010003;performance event-select (3)
+ EVENT_MASK:8
+ UNIT_MASK:8
+ USR:1
+ OS:1
+ E:1
+ PC:1
+ INT:1
+ :1
+ EN:1
+ INV:1
+ CNT_MASK:8
+ :32
+}
+
+{PerfCtr0=0xc0010004;performance counter (0)
+ CTR:48
+ :16
+}
+
+{PerfCtr1=0xc0010005;performance counter (1)
+ CTR:48
+ :16
+}
+
+{PerfCtr2=0xc0010006;performance counter (2)
+ CTR:48
+ :16
+}
+
+{PerfCtr3=0xc0010007;performance counter (3)
+ CTR:48
+ :16
+}
+
+{SYSCFG=0xc0010010;system configuration
+ SysAckLimit:5
+ SysVicLimit:3
+ SetDirtyEnE:1
+ SetDirtyEnS:1
+ SetDirtyEnO:1
+ ClVicBlkEn:1;;RevB and earlier
+ :4
+ ChxToDirtyDis:1
+ SysUcLockEn:1
+ MtrrFixDramEn:1
+ MtrrFixDramModeEn:1
+ MtrrVarDramEn:1
+ MtrrTom2En:1
+ Tom2ForceMemTypeWB:1;;K8 NPT
+ :41
+}
+
+{HWCR=0xc0010015;hardware configuration
+ SMMLOCK:1
+ SLOWFENCE:1
+ :1
+ TLBCACHEDIS:1
+ INVD_WBINVD:1
+ :1
+ FFDIS:1
+ DISLOCK:1
+ IGNNE_EM:1
+ :3
+ HLTXSPCYCEN:1
+ SMISPCYCDIS:1
+ RSMSPCYCDIS:1
+ SSEDIS:1
+ :1
+ WRAP32DIS:1
+ MCi_STATUS_WREN:1
+ :5
+ START_FID:6
+ :34
+}
+
+{IORRBase0=0xc0010016;base of variable I/O range (0)
+ :3
+ WrDram:1
+ RdDram:1
+ :7
+ Base:28
+ :24
+}
+
+{IORRMask0=0xc0010017;mask of variable I/O range (0)
+ :11
+ V:1
+ Mask:28
+ :24
+}
+
+{IORRBase1=0xc0010018;base of variable I/O range (1)
+ :3
+ WrDram:1
+ RdDram:1
+ :7
+ Base:28
+ :24
+}
+
+{IORRMask1=0xc0010019;mask of variable I/O range (1)
+ :11
+ V:1
+ Mask:28
+ :24
+}
+
+{TOP_MEM=0xc001001a;top of memory address
+ :23
+ TOM:17
+ :24
+}
+
+{TOP_MEM2=0xc001001d;second top of memory address
+ :23
+ TOM2:17
+ :24
+}
+
+{MANID=0xc001001e;manufacturing identification number
+ MinorRev:4
+ MajorRev:4
+ ReticleSite:2
+ :54
+}
+
+{NB_CFG=0xc001001f;northbridge configuration
+ :9
+ En/DisRefUseFreeBuf:1;;<RevD enable, >=RevD disable
+ :21
+ DisCohLdtCfg:1
+ :4
+ DisDatMsk:1
+ :6
+ DisThmlPfMonSmiinterupts:1
+ :1
+ DisUsSysMgtRqToNLdt:1
+ :8
+ InitApicIdCpuIdLo:1
+ :9
+}
+
+{ProcessorNameString0=0xc0010030;processor name string (0)
+ CpuNameString:64
+}
+
+{ProcessorNameString1=0xc0010031;processor name string (1)
+ CpuNameString:64
+}
+
+{ProcessorNameString2=0xc0010032;processor name string (2)
+ CpuNameString:64
+}
+
+{ProcessorNameString3=0xc0010033;processor name string (3)
+ CpuNameString:64
+}
+
+{ProcessorNameString4=0xc0010034;processor name string (4)
+ CpuNameString:64
+}
+
+{ProcessorNameString5=0xc0010035;processor name string (5)
+ CpuNameString:64
+}
+
+{HTC=0xc001003e;hardware thermal control
+ HtcEn:1
+ HtcSbcEn:1
+ :2
+ HtcAct:1
+ HtcActSts:1
+ :58
+} # K8 NPT only
+
+{ThermalControl=0xc001003f;thermal control
+ StcSbcTmpHiEn:1
+ StcSbcTmpLoEn:1
+ StcApcTmpHiEn:1
+ StcApcTmpLoEn:1
+ StcHtcEn:1
+ :1
+ StcTmpHiSts:1
+ StcTmpLoSts:1
+ :8
+ StcTmpLmt:5
+ :3
+ StcHystLmt:4
+ :36
+} # K8 NPT only
+
+{FIDVID_CTL=0xc0010041;FIDVID control
+ NewFID:6
+ :2
+ NewVID:6
+ :2
+ IniFidVid:1
+ :15
+ StpGntTOCnt:20
+ :12
+}
+
+# {FIDVID_STATUS=0xc0010042;FIDVID status
+# CurFID:6
+# :2
+# StartFID:6
+# :2
+# MaxFID:6
+# :2
+# MaxRampVID:5
+# :2
+# FidVidPending:1
+# CurVID:5
+# :3
+# StartVID:5
+# :3
+# MaxVID:5
+# :3
+# MinVID:5
+# :3
+# } # K8 non-NPT
+
+{FIDVID_STATUS=0xc0010042;FIDVID status
+ CurFID:6
+ :2
+ StartFID:6
+ :2
+ MaxFID:6
+ :2
+ MaxRampVID:6
+ :1
+ FidVidPending:1
+ CurVID:6
+ :2
+ StartVID:6
+ :2
+ MaxVID:6
+ :2
+ PstateStep:1
+ AltVidOffset:3
+ :1
+ IntPstateSup:1
+ :2
+} # K8 NPT
+
+{MC0_CTL_MASK=0xc0010044;data cache MC control mask
+ ECCI:1
+ ECCM:1
+ DECC:1
+ DMTP:1
+ DSTP:1
+ L1TP:1
+ L2TP:1
+ :57
+}
+
+{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask
+ ECCI:1
+ ECCM:1
+ IDP:1
+ IMTP:1
+ ISTP:1
+ L1TP:1
+ L2TP:1
+ :2
+ RDDE:1
+ :54
+}
+
+{MC2_CTL_MASK=0xc0010046;bus unit MC control mask
+ S_RDE_HP:1
+ S_RDE_TLB:1
+ S_RDE_ALL:1
+ S_ECC1_TLB:1
+ S_ECC1_HP:1
+ S_ECCM_TLB:1
+ S_ECCM_HP:1
+ L2T_PAR_ICDC:1
+ L2T_PAR_TLB:1
+ L2_PAR_SNP:1
+ L2_PAR_CPB:1
+ L2_PAR_SCR:1
+ L2D_ECC1_TLB:1
+ L2D_ECC1_SNP:1
+ L2D_ECC1_CPB:1
+ L2D_ECCM_TLB:1
+ L2D_ECCM_SNP:1
+ L2D_ECCM_CPB:1
+ L2T_ECC1_SCR:1
+ L2T_ECCM_SCR:1
+ :44
+}
+
+{MC3_CTL_MASK=0xc0010047;load store unit MC control mask
+ S_RDE_L:1
+ S_RDE_S:1
+ :62
+}
+
+{MC4_CTL_MASK=0xc0010048;northbridge MC control mask
+ CorrEccEn:1
+ UnCorrEccEn:1
+ CrcErr0En:1
+ CrcErr1En:1
+ CrcErr2En:1
+ SyncPkt0En:1
+ SyncPkt1En:1
+ SyncPkt2En:1
+ MstrAbrtEn:1
+ TgtAbrtEn:1
+ GartTblWkEn:1
+ AtomicRMWEn:1
+ WchDogTmrEn:1
+ :5
+ DramParEn:1
+ :45
+}
+
+{IOTRAP_ADDR0=0xc0010050;IO trap addr (0)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{IOTRAP_ADDR1=0xc0010051;IO trap addr (1)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{IOTRAP_ADDR2=0xc0010052;IO trap addr (2)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{IOTRAP_ADDR3=0xc0010053;IO trap addr (3)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{IOTRAP_CTL=0xc0010054;IO trap control
+ SmiSts_0:1
+ SmiEn_0:1
+ SmiSts_1:1
+ SmiEn_1:1
+ SmiSts_2:1
+ SmiEn_2:1
+ SmiSts_3:1
+ SmiEn_3:1
+ :5
+ IoTrapCtlRsmSpcEn:1
+ IoTrapCtlSmiSpcEn:1
+ IoTrapEn:1
+ :48
+}
+
+{IntPendingMessage=0xc0010055;interrupt pending message
+ IOMsgAddr:16
+ IOMsgData:8
+ IntrPndMsgDis:1
+ IntrPndMsg:1
+ IORd:1
+ SmiOnCmpHalt:1;;K8 NPT
+ C1eOnCmpHalt:1;;K8 NPT
+ :35
+}
+
+{SMM_BASE=0xc0010111;SMM base address
+ SMM_BASE:32
+ :32
+}
+
+{SMM_ADDR=0xc0010112;SMM TSeg base address
+ :17
+ ADDR:23
+ :24
+}
+
+{SMM_MASK=0xc0010113;SMM TSeg mask
+ AValid:1
+ TValid:1
+ AClose:1
+ TClose:1
+ AMTypeIoWc:1
+ TMTypeIoWc:1
+ :2
+ AMTypeDram:3
+ :1
+ TMTypeDram:3
+ :2
+ MASK:23
+ :24
+}
+
+{VM_CR=0xc0010114;security related controls
+ dpd:1
+ r_init:1
+ dis_a20m:1
+ LOCK:1
+ SVME_DISABLE:1
+ :59
+} # K8 NPT only
+
+{VM_HSAVE_PA=0xc0010117;VM host save physical address
+ VM_HSAVE_PA:64
+} # K8 NPT only
+
+### Local Variables: ###
+### mode:shell-script ###
+### End: ###
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/powernow.c
^
|
| @@ -1,12 +1,9 @@
/*
- * $Id: powernow.c,v 1.10 2003/03/11 13:57:39 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
- * AMD-specific information
- *
+ * Decode powernow registers.
*/
#include <stdio.h>
@@ -71,9 +68,9 @@
fid_codes[fidvidstatus.bits.SFID],
fid_codes[fidvidstatus.bits.CFID]);
-// printf ("Voltage ID codes: Maximum=0x%x Startup=0x%x Currently=0x%x\n",
+// printf("Voltage ID codes: Maximum=0x%x Startup=0x%x Currently=0x%x\n",
// fidvidstatus.MVID, fidvidstatus.SVID, fidvidstatus.CVID);
-// printf ("Frequency ID codes: Maximum=0x%x Startup=0x%x Currently=0x%x\n",
+// printf("Frequency ID codes: Maximum=0x%x Startup=0x%x Currently=0x%x\n",
// fidvidstatus.MFID, fidvidstatus.SFID, fidvidstatus.CFID);
if (show_bios) {
@@ -105,7 +102,7 @@
printf("\n");
if (read_msr(cpu->number, MSR_FID_VID_STATUS, &fidvidstatus.val) != 1) {
- printf ("Something went wrong reading MSR_FID_VID_STATUS\n");
+ printf("Something went wrong reading MSR_FID_VID_STATUS\n");
return;
}
@@ -164,7 +161,7 @@
void decode_powernow(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
int can_scale_vid=0, can_scale_fid=0;
if (cpu->maxei < 0x80000007)
@@ -185,19 +182,19 @@
can_scale_vid=1;
}
if (edx & (1<<3))
- printf ("\n\tThermal Trip");
+ printf("\n\tThermal Trip");
if (edx & (1<<4))
- printf ("\n\tThermal Monitoring");
+ printf("\n\tThermal Monitoring");
if (edx & (1<<5))
- printf ("\n\tSoftware Thermal Control");
+ printf("\n\tSoftware Thermal Control");
if (edx & (1<<6))
- printf ("\n\t100MHz multiplier control");
+ printf("\n\t100MHz multiplier control");
if (edx & (1<<7)) {
- printf ("\n\tHardware P-state control");
+ printf("\n\tHardware P-state control");
can_scale_fid = can_scale_vid = 1;
}
if (edx & (1<<8))
- printf ("\n\tinvariant TSC");
+ printf("\n\tinvariant TSC");
if (!(edx & 0x1f))
printf(" None");
printf("\n\n");
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/powernow.h
^
|
| @@ -1,12 +1,9 @@
/*
- * $Id: powernow.h,v 1.4 2003/01/16 17:09:18 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
- * AMD-specific information
- *
+ * Powernow register definitions.
*/
#include <sys/types.h>
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/AMD/revision.h
^
|
| @@ -16,24 +16,28 @@
#define _ATHLON64 0x0004
#define _ATHLON64_X2 0x0008
#define _ATHLON64_FX 0x0010
-#define _ATHLON64_M 0x0020
-#define _SEMPRON 0x0040
-#define _SEMPRON_M 0x0080
-#define _ATHLON_XPM 0x0100
-#define _TURION 0x0200
-#define _TURION_X2 0x0400
+#define _ATHLON64_FX_DC 0x0020
+#define _ATHLON64_M 0x0040
+#define _SEMPRON 0x0080
+#define _SEMPRON_M 0x0100
+#define _ATHLON_XPM 0x0200
+#define _TURION 0x0400
+#define _TURION_X2 0x0800
struct id_string {
int id;
const char *name;
};
+/* Note: For newer K8 NPT parts naming switched from "Athlon 64"
+ to "Athlon" etc., but we stick to the old naming here. */
struct id_string k8_names[] = {
{_OPTERON, "Opteron"},
{_OPTERON_DC, "Dual-Core Opteron"},
{_ATHLON64, "Athlon 64"},
{_ATHLON64_X2, "Athlon 64 X2 Dual-Core"},
{_ATHLON64_FX, "Athlon 64 FX"},
+ {_ATHLON64_FX_DC, "Athlon 64 FX Dual-Core"},
{_ATHLON64_M, "Mobile Athlon 64"},
{_SEMPRON, "Sempron"},
{_SEMPRON_M, "Mobile Sempron"},
@@ -91,18 +95,51 @@
{0x20ff2, CONN_SOCKET_939, _ATHLON64|_SEMPRON, "DH-E6"},
{0x20f12, CONN_SOCKET_940, _OPTERON_DC, "JH-E6"},
{0x20f32, CONN_SOCKET_939, _OPTERON_DC|_ATHLON64_X2, "JH-E6"},
+
+ /* K8 NPT */
{0x40f12, CONN_SOCKET_F, _OPTERON_DC, "JH-F2"},
- {0x40f32, CONN_SOCKET_AM2, _ATHLON64_X2|_OPTERON_DC, "JH-F2"},
+ {0x40f13, CONN_SOCKET_F, _OPTERON_DC, "JH-F3"},
+ {0x40f32, CONN_SOCKET_AM2,
+ _ATHLON64_X2|_ATHLON64_FX_DC|_OPTERON_DC, "JH-F2"},
+ {0x40f33, CONN_SOCKET_AM2,
+ _ATHLON64_X2|_ATHLON64_FX_DC|_OPTERON_DC, "JH-F3"},
{0x40f82, CONN_SOCKET_S1G1, _TURION_X2, "BH-F2"},
{0x40fb2, CONN_SOCKET_AM2, _ATHLON64_X2, "BH-F2"},
- {0x40ff2, CONN_SOCKET_AM2, _SEMPRON|_ATHLON64, "DH-F2"},
- {0x50ff2, CONN_SOCKET_AM2, _SEMPRON|_ATHLON64, "DH-F2"},
+ {0x40fc2, CONN_SOCKET_S1G1,_ATHLON64|_SEMPRON|_SEMPRON_M, "DH-F2"},
+ {0x40ff2, CONN_SOCKET_AM2, _ATHLON64|_SEMPRON, "DH-F2"},
+ {0x50ff2, CONN_SOCKET_AM2, _ATHLON64|_SEMPRON, "DH-F2"},
+ {0x50ff3, CONN_SOCKET_AM2, _ATHLON64, "DH-F3"},
+ {0x60f81, CONN_SOCKET_S1G1,_ATHLON64_X2, "BH-G1"},
+ {0x60f82, CONN_SOCKET_S1G1,_ATHLON64_X2|_TURION_X2, "BH-G2"},
+ {0x60fb1, CONN_SOCKET_AM2,_ATHLON64_X2, "BH-G1"},
+ {0x60fb2, CONN_SOCKET_AM2,_ATHLON64_X2, "BH-G2"},
+ {0x60fc2, CONN_SOCKET_S1G1,_SEMPRON_M, "DH-G2"},
+ {0x60ff2, CONN_SOCKET_AM2,_SEMPRON|_ATHLON64, "DH-G2"},
+ {0x70fc2, CONN_SOCKET_S1G1,_SEMPRON_M, "DH-G2"},
+ {0x70ff1, CONN_SOCKET_AM2,_SEMPRON|_ATHLON64, "DH-G1"},
+ {0x70ff2, CONN_SOCKET_AM2,_SEMPRON, "DH-G2"},
+ {0xc0f13, CONN_SOCKET_F, _ATHLON64_FX, "JH-F3"},
+};
+
+#define _OPTERON 0x0001
+#define _PHENOM 0x0002
+
+struct fam10h_rev {
+ int eax;
+ int nameid;
+ const char* rev;
+};
+
+struct fam10h_rev fam10h_revisions[] = {
+ {0x0100f2a, _OPTERON, "DR-BA"},
+ {0x0100f22, _OPTERON|_PHENOM, "DR-B2"},
+ {0x0100f23, _OPTERON|_PHENOM, "DR-B3"},
+ {0x0100f42, _OPTERON, "RB-C2"},
};
-struct id_string fam10h_revisions[] = {
- {0x0100f2a, "DR-BA"},
- {0x0100f22, "DR-B2"},
+struct id_string fam11h_revisions[] = {
+ {0x0200f31, "LG-B1"},
};
-get_name(fam10h_revision, int, fam10h_revisions);
+get_name(fam11h_revision, int, fam11h_revisions);
#endif /* _amd_revision_h_ */
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur
^
|
| +(directory)
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/MSR-C3.c
^
|
| @@ -0,0 +1,30 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Centaur specific parts.
+ */
+#include <stdio.h>
+#include "../x86info.h"
+#include "centaur.h"
+
+void dump_C3_MSR (struct cpudata *cpu)
+{
+ if (!user_is_root)
+ return;
+
+ printf("FCR: ");
+ dumpmsr (cpu->number, 0x1107, 32);
+
+ printf("Power management: ");
+ if (cpu->model==6 || cpu->model==7) {
+ printf("Longhaul\n");
+ decode_longhaul(cpu);
+ }
+
+ if (cpu->model==8 || cpu->model==9) {
+ printf("Powersaver\n");
+ decode_powersaver(cpu);
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/centaur.h
^
|
| @@ -0,0 +1,6 @@
+#ifndef _CENTAUR_H
+#define _CENTAUR_H
+void dump_C3_MSR (struct cpudata *cpu);
+void decode_longhaul(struct cpudata *cpu);
+void decode_powersaver(struct cpudata *cpu);
+#endif /* _CENTAUR_H */
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/identify.c
^
|
| @@ -0,0 +1,171 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Centaur specific parts.
+ */
+#include <stdio.h>
+#include "../x86info.h"
+#include "centaur.h"
+
+static char *centaur_nameptr;
+#define add_to_cpuname(x) centaur_nameptr += snprintf(centaur_nameptr, sizeof(x), "%s", x);
+
+void identify_centaur(struct cpudata *cpu)
+{
+ char *nameptr;
+
+ centaur_nameptr = nameptr = cpu->name;
+
+ switch (tuple(cpu) & 0xff0) {
+ case 0x540:
+ add_to_cpuname("Winchip C6");
+ //transistors = 5400000;
+ //fab_process = "0.35 micron CMOS";
+ //die_size = "88 sq.mm";
+ //introduction_date = "September 1997";
+ //pipeline_stages = 6;
+ break;
+ case 0x580:
+ switch (cpu->stepping) {
+ case 0 ... 6:
+ add_to_cpuname("Winchip 2");
+ break;
+ case 7 ... 9:
+ add_to_cpuname("Winchip 2A");
+ break;
+ case 0xA ... 0xF:
+ add_to_cpuname("Winchip 2B");
+ break;
+ }
+ break;
+ case 0x590:
+ add_to_cpuname("Winchip 3");
+ break;
+
+ /* Family 6 is when VIA bought out Cyrix & Centaur
+ * This is the CyrixIII family. */
+ case 0x660:
+ add_to_cpuname("VIA Cyrix 3 (Samuel) [C5A]");
+ //pipeline_stages = 12;
+ //1.8-2.0V
+ //CPGA
+ //75mm
+ //0.18 Al
+ //500-733MHz
+ //11.3 mil transistors
+ //June 6 2000
+ break;
+ case 0x670:
+ switch (cpu->stepping) {
+ case 0 ... 7:
+ add_to_cpuname("VIA C3 (Samuel 2) [C5B]");
+ //pipeline_stages = 12;
+ //1.6V
+ //CPGA/EBGA
+ //52mm
+ //0.15u Al
+ //650-800MHz
+ //15.2 mil transistors
+ //Mar 25 2001
+ break;
+ case 8 ... 0xf:
+ add_to_cpuname("VIA C3 (Ezra) [C5C]");
+ //pipeline_stages = 12;
+ //1.35V
+ //CPGA/EBGA
+ //52mm
+ //0.15u/0.13u hybrid Al
+ //800-1000MHz
+ //15.4 mil transistors
+ //Sep 11 2001
+ break;
+ }
+ break;
+ /* Ezra-T is much like Ezra but reworked to run in Pentium III Tualatin sockets. */
+ case 0x680: add_to_cpuname("VIA C3 (Ezra-T) [C5M/C5N]");
+ //pipeline_stages = 12;
+ //CPGA/EBGA/uPGA2/uFCPGA
+ //900-1200MHz
+ //56mm
+ //0.15/0.13u hybrid (Cu)
+ //15.5 mil transistors
+ //C5N=copper interconnectrs
+ //2002
+ break;
+ case 0x690: add_to_cpuname("VIA C3 (Nehemiah) [C5XL]");
+ //pipeline_stages = 16;
+ //2 SSE units
+ //first C3 to run FPU at full clock speed (previous ran at 50%)
+ //1100-1300
+ //0.13 (Cu)
+ //die_size = "78 sq. mm"; (C5X)
+ //die_size = "54 sq. mm"; (C5XL)
+ //January 22 2003
+ break;
+ case 0x6A0: switch (cpu->stepping) {
+ case 0:
+ case 8 ... 0xF:
+ add_to_cpuname("VIA C3 (Esther) [C7-M]");
+ break;
+ case 1 ... 7:
+ add_to_cpuname("VIA C3 (Ruth) [C7-M]");
+ break;
+ }
+ break;
+
+ // C5P introduced the HW AES
+ // C5YL
+ // C5X
+ // CZA
+
+ default:
+ add_to_cpuname("Unknown VIA CPU");
+ break;
+ }
+}
+
+
+static void decode_centaur_cacheinfo(struct cpudata *cpu)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ if (cpu->maxei >= 0x80000005) {
+ /* TLB and cache info */
+ cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx);
+ printf("Cache info\n");
+ printf(" L1 Instruction cache: %dKB, %d-way associative, %d lines per tag, line size=%d bytes.\n",
+ edx >> 24, (edx >> 16) & 0xff, (edx >> 8) & 0xff, edx & 0xff);
+ printf(" L1 Data cache: %dKB %d-way associative, %d lines per tag, line size=%d bytes.\n",
+ ecx >> 24, (ecx >> 16) & 0xff, (ecx >> 8) & 0xff, ecx & 0xff);
+ if (cpu->maxei >= 0x80000006) {
+ cpuid (cpu->number, 0x80000006, &eax, &ebx, &ecx, &edx);
+ if ((cpu->family==6) && (cpu->model==7 || cpu->model==8))
+ /* Work around errata. */
+ printf(" L2 (on CPU) cache: %dKB %d-way associative, %d lines per tag, line size=%d bytes.\n",
+ ecx >> 24, (ecx >> 16) & 0x0f, (ecx >> 8) & 0x0f, ecx & 0xff);
+ else
+ printf(" L2 (on CPU) cache: %dKB %d-way associative, %d lines per tag, line size=%d bytes.\n",
+ ecx >> 16, (ecx >> 12) & 0x0f, (ecx >> 8) & 0x0f, ecx & 0xff);
+ }
+ printf("TLB info\n");
+ cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx);
+ printf(" Instruction TLB: %d-way associative. %d entries.\n", (ebx >> 8) & 0xff, ebx & 0xff);
+ printf(" Data TLB: %d-way associative. %d entries.\n", ebx >> 24, (ebx >> 16) & 0xff);
+ }
+
+ /* check on-chip L2 cache size */
+}
+
+
+void display_centaur_info(struct cpudata *cpu)
+{
+ if (cpu->maxei == 0)
+ return;
+
+ decode_centaur_cacheinfo(cpu);
+
+ if (cpu->family == 6 && show_registers)
+ dump_C3_MSR(cpu);
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/longhaul-v2.c
^
|
| @@ -0,0 +1,84 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Longhaul v2 register definitions.
+ */
+#include <stdio.h>
+#include "../x86info.h"
+
+union msr_longhaul {
+ struct {
+ unsigned RevisionID:4, // 3:0
+ RevisionKey:4, // 7:4
+ EnableSoftBusRatio:1, // 8
+ EnableSoftVID:1, // 9
+ EnableSoftBSEL:1, // 10
+ Reserved:3, // 11:13
+ SoftBusRatio4:1, // 14
+ VRMRev:1, // 15
+ SoftBusRatio:4, // 19:16
+ SoftVID:5, // 24:20
+ Reserved2:3, // 27:25
+ SoftBSEL:2, // 29:28
+ Reserved3:2, // 31:30
+ MaxMHzBR:4, // 35:32
+ MaximumVID:5, // 40:36
+ MaxMHzFSB:2, // 42:41
+ MaxMHzBR4:1, // 43
+ Reserved4:4, // 47:44
+ MinMHzBR:4, // 51:48
+ MinimumVID:5, // 56:52
+ MinMHzFSB:2, // 58:57
+ MinMHzBR4:1, // 59
+ Reserved5:4; // 63:60
+ } bits;
+ unsigned long long val;
+};
+
+void decode_longhaul2(struct cpudata *cpu)
+{
+ union msr_longhaul longhaul;
+
+ if (read_msr(cpu->number, 0x110A, &longhaul.val) == 1) {
+ dumpmsr (cpu->number, 0x110A, 64);
+
+ if (longhaul.bits.RevisionID & 1)
+ printf("\tSoftVID support\n");
+ if (longhaul.bits.RevisionID & 2)
+ printf("\tSoftBSEL support\n");
+ if (longhaul.bits.RevisionID == 0)
+ printf("\tSoftware clock multiplier only: No Softvid\n");
+
+ if (longhaul.bits.EnableSoftBusRatio==1)
+ printf("\tEnableSoftBusRatio=Enabled\n");
+ if (longhaul.bits.EnableSoftVID==1)
+ printf("\tEnableSoftVID=Enabled\n");
+ if (longhaul.bits.EnableSoftBSEL==1)
+ printf("\tEnableSoftBSEL=Enabled\n");
+
+ printf("\tSoftBusRatio4=%s\n", longhaul.bits.SoftBusRatio4 ? "1" : "0");
+ printf("\tSoftBusRatio=");
+ binary (4, longhaul.bits.SoftBusRatio);
+
+ if (longhaul.bits.RevisionID & 1)
+ printf("\tVRM Rev=%s\n",
+ longhaul.bits.VRMRev ? "Mobile VRM" : "VRM 8.5");
+
+ printf("\tMaxMHzBR4: %s\n", longhaul.bits.MaxMHzBR4 ? "1" : "0");
+ printf("\tMaxMHzBR: ");
+ binary (4, longhaul.bits.MaxMHzBR);
+ printf("\tMaximumVID: ");
+ binary (5, longhaul.bits.MaximumVID);
+ printf("\tMaxMHzFSB: ");
+ binary (2, longhaul.bits.MaxMHzFSB);
+ printf("\tMinMHzBR4: %s\n", longhaul.bits.MinMHzBR4 ? "1" : "0");
+ printf("\tMinMHzBR: ");
+ binary (4, longhaul.bits.MinMHzBR);
+ printf("\tMinimumVID: ");
+ binary (4, longhaul.bits.MinimumVID);
+ printf("\tMinMHzFSB: ");
+ binary (2, longhaul.bits.MinMHzFSB);
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/longhaul.c
^
|
| @@ -0,0 +1,85 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Longhaul register decoding.
+ */
+#include <stdio.h>
+#include "../x86info.h"
+#include "centaur.h"
+
+union msr_longhaul {
+ struct {
+ unsigned RevisionID:4, // 3:0
+ RevisionKey:4, // 7:4
+ EnableSoftBusRatio:1, // 8
+ EnableSoftVID:1, // 9
+ EnableSoftBSEL:1, // 10
+ Reserved:3, // 11:13
+ SoftBusRatio4:1, // 14
+ VRMRev:1, // 15
+ SoftBusRatio:4, // 19:16
+ SoftVID:5, // 24:20
+ Reserved2:3, // 27:25
+ SoftBSEL:2, // 29:28
+ Reserved3:2, // 31:30
+ MaxMHzBR:4, // 35:32
+ MaximumVID:5, // 40:36
+ MaxMHzFSB:2, // 42:41
+ MaxMHzBR4:1, // 43
+ Reserved4:4, // 47:44
+ MinMHzBR:4, // 51:48
+ MinimumVID:5, // 56:52
+ MinMHzFSB:2, // 58:57
+ MinMHzBR4:1, // 59
+ Reserved5:4; // 63:60
+ } bits;
+ unsigned long long val;
+};
+
+void decode_longhaul(struct cpudata *cpu)
+{
+ union msr_longhaul longhaul;
+
+ if (read_msr(cpu->number, 0x110A, &longhaul.val) == 1) {
+ dumpmsr (cpu->number, 0x110A, 64);
+
+ if (longhaul.bits.RevisionID & 1)
+ printf("\tSoftVID support\n");
+ if (longhaul.bits.RevisionID & 2)
+ printf("\tSoftBSEL support\n");
+ if (longhaul.bits.RevisionID == 0)
+ printf("\tSoftware clock multiplier only: No Softvid\n");
+
+ if (longhaul.bits.EnableSoftBusRatio==1)
+ printf("\tEnableSoftBusRatio=Enabled\n");
+ if (longhaul.bits.EnableSoftVID==1)
+ printf("\tEnableSoftVID=Enabled\n");
+ if (longhaul.bits.EnableSoftBSEL==1)
+ printf("\tEnableSoftBSEL=Enabled\n");
+
+ printf("\tSoftBusRatio4=%s\n", longhaul.bits.SoftBusRatio4 ? "1" : "0");
+ printf("\tSoftBusRatio=");
+ binary (4, longhaul.bits.SoftBusRatio);
+
+ if (longhaul.bits.RevisionID & 1)
+ printf("\tVRM Rev=%s\n",
+ longhaul.bits.VRMRev ? "Mobile VRM" : "VRM 8.5");
+
+ printf("\tMaxMHzBR4: %s\n", longhaul.bits.MaxMHzBR4 ? "1" : "0");
+ printf("\tMaxMHzBR: ");
+ binary (4, longhaul.bits.MaxMHzBR);
+ printf("\tMaximumVID: ");
+ binary (5, longhaul.bits.MaximumVID);
+ printf("\tMaxMHzFSB: ");
+ binary (2, longhaul.bits.MaxMHzFSB);
+ printf("\tMinMHzBR4: %s\n", longhaul.bits.MinMHzBR4 ? "1" : "0");
+ printf("\tMinMHzBR: ");
+ binary (4, longhaul.bits.MinMHzBR);
+ printf("\tMinimumVID: ");
+ binary (4, longhaul.bits.MinimumVID);
+ printf("\tMinMHzFSB: ");
+ binary (2, longhaul.bits.MinMHzFSB);
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/powersaver.c
^
|
| @@ -0,0 +1,84 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Powersaver MSR decoding.
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "centaur.h"
+#include "powersaver.h"
+
+void decode_powersaver(struct cpudata *cpu)
+{
+ union msr_powersaver ps;
+
+ if (!user_is_root)
+ return;
+
+ dumpmsr(cpu->number, MSR_POWERSAVER, 64);
+ printf("\n");
+
+ if (read_msr(cpu->number, MSR_POWERSAVER, &ps.val) != 1) {
+ printf("Something went wrong reading MSR_POWERSAVER\n");
+ return;
+ }
+
+ printf(" RevisionID: %x : ", ps.bits.RevisionID);
+ switch (ps.bits.RevisionID) {
+ case 0x0: printf("Initial revision (Software clock multiplier only, no SoftVID)\n");
+ break;
+ case 0x1: printf("SoftVID support\n");
+ break;
+ default: printf("Unknown (0x%x).\n", ps.bits.RevisionID);
+ break;
+ }
+
+ printf(" Software clock multiplier is ");
+ if (ps.bits.EnableSoftBusRatio == 0)
+ printf("disabled\n");
+ else {
+ printf("enabled\n");
+ printf("\tMaxMHzBR4: %s\n", ps.bits.MaxMHzBR4 ? "1" : "0");
+ printf("\tMaxMHzBR: ");
+ binary (4, ps.bits.MaxMHzBR);
+ printf("\tMinMHzBR4: %s\n", ps.bits.MinMHzBR4 ? "1" : "0");
+ printf("\tMinMHzBR: ");
+ binary (4, ps.bits.MinMHzBR);
+ }
+
+ /* these bits invalid if revision == 0*/
+ if (ps.bits.RevisionID != 0) {
+ printf(" Software VID is ");
+ if (ps.bits.EnableSoftVID == 0)
+ printf("disabled\n");
+ else {
+ printf("enabled\n");
+ printf("\tVRM Rev=%s\n",
+ ps.bits.VRMRev ? "Mobile VRM" : "VRM 8.5");
+ printf("\tMinimumVID: ");
+ binary (4, ps.bits.MinimumVID);
+ printf("\tMaximumVID: ");
+ binary (5, ps.bits.MaximumVID);
+ }
+
+ if (ps.bits.EnableSoftBusRatio==1) {
+ printf("\tEnableSoftBusRatio=Enabled\n");
+ printf("\tMaxMHzFSB: ");
+ binary (2, ps.bits.MaxMHzFSB);
+ printf("\tMinMHzFSB: ");
+ binary (2, ps.bits.MinMHzFSB);
+ }
+
+ //if (ps.bits.EnableSoftBSEL==1)
+ // printf("\tEnableSoftBSEL=Enabled\n");
+
+ printf("\tSoftBusRatio4=%s\n", ps.bits.SoftBusRatio4 ? "1" : "0");
+ printf("\tSoftBusRatio=");
+ binary (4, ps.bits.SoftBusRatio);
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Centaur/powersaver.h
^
|
| @@ -0,0 +1,38 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Powersaver MSR definitions.
+ */
+
+#include <sys/types.h>
+
+#define MSR_POWERSAVER 0x110a
+
+union msr_powersaver {
+ struct {
+ unsigned RevisionID:4, // 3:0
+ RevisionKey:4, // 7:4
+ EnableSoftBusRatio:1, // 8
+ EnableSoftVID:1, // 9
+ Reserved:4, // 10:13
+ SoftBusRatio4:1, // 14
+ VRMRev:1, // 15
+ SoftBusRatio:4, // 16:19
+ SoftVID:5, // 20:24
+ Reserved2:7, // 25:31
+ MaxMHzBR:4, // 32:35
+ MaximumVID:5, // 36:40
+ MaxMHzFSB:2, // 41:42
+ MaxMHzBR4:1, // 43
+ Reserved3:4, // 44:47
+ MinMHzBR:4, // 48:51
+ MinimumVID:5, // 52:56
+ MinMHzFSB:2, // 57:58
+ MinMHzBR4:1, // 59
+ Reserved4:4; // 60:63
+ } bits;
+ unsigned long long val;
+};
+
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Cyrix/identify.c
^
|
| @@ -1,11 +1,9 @@
/*
- * $Id: identify.c,v 1.14 2002/11/11 20:02:55 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
- * Cyrix bits.
+ * Cyrix specific information.
*/
#include <stdio.h>
@@ -22,46 +20,36 @@
case 0:
break;
case 0x70:
- printf ("TLB: 32 entries 4-way associative 4KB pages\n");
+ printf("TLB: 32 entries 4-way associative 4KB pages\n");
break;
case 0x80:
- printf ("L1 Cache: 16KB 4-way associative 16 bytes/line\n");
+ printf("L1 Cache: 16KB 4-way associative 16 bytes/line\n");
break;
}
}
/* Cyrix-specific information */
-void Identify_Cyrix (struct cpudata *cpu)
+void Identify_Cyrix(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
cyrix_nameptr = cpu->name;
- cpu->vendor = VENDOR_CYRIX;
-
- /* Do standard stuff */
- if (cpu->maxi < 1)
- return;
-
- cpuid (cpu->number, 1, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
switch (tuple(cpu) & 0xff0) {
case 0x450: add_to_cpuname("MediaGX");
- break;
+ break;
case 0x520: add_to_cpuname("6x86");
- break;
+ break;
case 0x524: add_to_cpuname("GXm");
- break;
+ break;
case 0x600: add_to_cpuname("6x86/MX");
- break;
+ break;
case 0x620: add_to_cpuname("MII");
- break;
+ break;
default: add_to_cpuname("Unknown CPU");
- break;
+ break;
}
/* Check for presence of extended info */
@@ -88,16 +76,9 @@
void display_Cyrix_info(struct cpudata *cpu)
{
unsigned int i, ntlb;
- unsigned long eax, ebx, ecx, edx;
-
- printf ("Family: %u Model: %u Stepping: %u\n",
- cpu->family, cpu->model, cpu->stepping);
- printf ("CPU Model : %s\n", cpu->name);
- get_model_name (cpu);
-
- decode_feature_flags (cpu);
+ unsigned int eax, ebx, ecx, edx;
- printf ("TLB & L1 Cache info\n");
+ printf("TLB & L1 Cache info\n");
if (cpu->maxi >= 2 && show_cacheinfo) {
/* TLB and L1 Cache info */
ntlb = 255;
@@ -118,7 +99,7 @@
}
}
- printf ("TLB & L1 Cache info from extended info\n");
+ printf("TLB & L1 Cache info from extended info\n");
if (cpu->maxei >= 0x80000005 && show_cacheinfo) {
/* TLB and L1 Cache info */
ntlb = 255;
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/Intel.h
^
|
| @@ -7,6 +7,9 @@
extern void dump_p6_MSRs(struct cpudata *cpu);
extern void dump_centrino_MSRs(struct cpudata *cpu);
extern void decode_microcode(struct cpudata *cpu);
+extern void Identify_Intel_family6pentium(struct cpudata *cpu);
+extern void Identify_Intel_family6core(struct cpudata *cpu);
+extern void Identify_Intel_family15(struct cpudata *cpu);
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_IA32_UCODE_REV 0x8b
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/MSR-P4.c
^
|
| @@ -1,119 +1,117 @@
/*
- * $Id: MSR-P4.c,v 1.2 2003/04/11 00:17:20 davej Exp $
- * This file is part of x86info.
* (C) 2002 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Intel P4 specific MSR information
* See 24547203.pdf for more details.
- *
*/
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include "../x86info.h"
+#include "Intel.h"
void dump_p4_MSRs (struct cpudata *cpu)
{
- unsigned long long val=0;
+ unsigned long long val = 0;
if (!user_is_root)
return;
- printf ("Pentium 4 specific MSRs:\n");
+ printf("Pentium 4 specific MSRs:\n");
- if (read_msr (cpu->number, 0x17, &val)==1)
- printf ("IA32_PLATFORM_ID=%016llx\n", val);
+ if (read_msr (cpu->number, 0x17, &val) == 1)
+ printf("IA32_PLATFORM_ID=%016llx\n", val);
- if (read_msr (cpu->number, 0x2a, &val)==1) {
- printf ("System bus in order queue depth=");
+ if (read_msr (cpu->number, 0x2a, &val) == 1) {
+ printf("System bus in order queue depth=");
if ((val & (1<<2)))
- printf ("1");
+ printf("1");
else
- printf ("12");
- printf ("\n");
+ printf("12");
+ printf("\n");
}
- if (read_msr (cpu->number, 0x2c, &val)==1) {
- printf ("MSR_EBC_FREQUENCY_ID=%016llx\n", val);
+ if (read_msr (cpu->number, 0x2c, &val) == 1) {
+ printf("MSR_EBC_FREQUENCY_ID=%016llx\n", val);
}
- if (read_msr (cpu->number, 0x8b, &val)==1) {
- printf ("IA32_BIOS_SIGN_ID=%016llx\n", val);
+ if (read_msr (cpu->number, 0x8b, &val) == 1) {
+ printf("IA32_BIOS_SIGN_ID=%016llx\n", val);
}
- if (read_msr (cpu->number, 0x119, &val)==1) {
- printf ("Processor serial number is ");
+ if (read_msr (cpu->number, 0x119, &val) == 1) {
+ printf("Processor serial number is ");
if ((val & (1<<21)))
- printf ("dis");
+ printf("dis");
else
- printf ("en");
- printf ("abled\n");
+ printf("en");
+ printf("abled\n");
}
- if (read_msr (cpu->number, 0x1a0, &val)==1) {
- printf ("Fast string enable is ");
+ if (read_msr (cpu->number, 0x1a0, &val) == 1) {
+ printf("Fast string enable is ");
if (!(val & (1<<0)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("x87 FPU Fopcode compatability mode is ");
+ printf("x87 FPU Fopcode compatability mode is ");
if (!(val & (1<<2)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("Thermal monitor enable is ");
+ printf("Thermal monitor enable is ");
if (!(val & (1<<3)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("Split lock disable is ");
+ printf("Split lock disable is ");
if (!(val & (1<<4)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("L3 cache disable is ");
+ printf("L3 cache disable is ");
if (!(val & (1<<6)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("Performance monitoring is ");
+ printf("Performance monitoring is ");
if (!(val & (1<<7)))
- printf ("un");
- printf ("available\n");
+ printf("un");
+ printf("available\n");
- printf ("Suppress lock enable is ");
+ printf("Suppress lock enable is ");
if (!(val & (1<<8)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("Prefetch queue disable is ");
+ printf("Prefetch queue disable is ");
if (!(val & (1<<9)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("FERR# Interrupt reporting enable is ");
+ printf("FERR# Interrupt reporting enable is ");
if (!(val & (1<<10)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("Branch trace storage unavailable is ");
+ printf("Branch trace storage unavailable is ");
if (!(val & (1<<11)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
- printf ("Precise Event Based Sampling Unavailable is ");
+ printf("Precise Event Based Sampling Unavailable is ");
if (!(val & (1<<12)))
- printf ("un");
- printf ("set\n");
+ printf("un");
+ printf("set\n");
}
/*
- if (read_msr (cpu->number, 0x410, &val)==1) {
+ if (read_msr (cpu->number, 0x410, &val) == 1) {
}
*/
- printf ("\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/MSR-P6.c
^
|
| @@ -1,42 +1,40 @@
/*
- * $Id: MSR-P6.c,v 1.1 2002/11/12 17:19:17 davej Exp $
- * This file is part of x86info.
* (C) 2002 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Intel P6 specific MSR information
* See 24547203.pdf for more details.
- *
*/
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include "../x86info.h"
+#include "Intel.h"
void dump_p6_MSRs (struct cpudata *cpu)
{
- unsigned long long val=0;
+ unsigned long long val = 0;
if (!user_is_root)
return;
- printf ("P6 family MSRs:\n");
+ printf("P6 family MSRs:\n");
- if (read_msr (cpu->number, 0x2a, &val)==1) {
- printf ("Low power mode is ");
- if ((val & (1<<26))==0)
- printf ("dis");
+ if (read_msr (cpu->number, 0x2a, &val) == 1) {
+ printf("Low power mode is ");
+ if ((val & (1<<26)) == 0)
+ printf("dis");
else
- printf ("en");
- printf ("abled\n");
+ printf("en");
+ printf("abled\n");
}
/*
- if (read_msr (cpu->number, 0x410, &val)==1) {
+ if (read_msr (cpu->number, 0x410, &val) == 1) {
}
*/
- printf ("\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/MSR-PM.c
^
|
| @@ -1,13 +1,10 @@
/*
- * $Id: MSR-PM.c,v 1.4 2003/06/12 05:56:10 davej Exp $
- * This file is part of x86info.
* (C) 2002 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Intel Pentium M specific MSR information
* See 24547203.pdf for more details.
- *
*/
#include <stdio.h>
@@ -18,15 +15,15 @@
void dump_centrino_MSRs (struct cpudata *cpu)
{
- unsigned long long val=0;
+ unsigned long long val = 0;
int tcc = 0;
if (!user_is_root)
return;
- printf ("Pentium M MSRs:\n");
+ printf("Pentium M MSRs:\n");
- if (read_msr (cpu->number, MSR_IA32_PERF_STATUS, &val)==1) {
+ if (read_msr (cpu->number, MSR_IA32_PERF_STATUS, &val) == 1) {
/*
Voltage and frequency values derived from 1300MHz
Pentium M in an IBM ThinkPad X31. Constants for
@@ -42,11 +39,11 @@
unsigned uv = (unsigned)val & 0xffff;
int volt = (uv & 0xff) * 16 + 700;
int mhz = 100 * (uv & 0xff00) >> 8UL;
- printf (" Current performance mode is 0x%04x: %dMHz, %d.%dV\n",
+ printf(" Current performance mode is 0x%04x: %dMHz, %d.%dV\n",
uv, mhz, volt/1000, volt%1000);
}
- if (read_msr (cpu->number, MSR_IA32_MISC_ENABLE, &val)==1) {
- printf (" Enabled: ");
+ if (read_msr (cpu->number, MSR_IA32_MISC_ENABLE, &val) == 1) {
+ printf(" Enabled: ");
if (val & (1<<3)) {
printf("TCC ");
tcc = 1;
@@ -64,17 +61,17 @@
printf("\n");
}
- if (tcc && read_msr (cpu->number, MSR_PM_THERM2_CTL, &val)==1) { /* THERM2_CTL */
+ if (tcc && read_msr (cpu->number, MSR_PM_THERM2_CTL, &val) == 1) { /* THERM2_CTL */
printf(" Thermal monitor %d\n", (val & (1<<16)) ? 2 : 1);
}
- if (read_msr (cpu->number, MSR_IA32_THERM_CONTROL, &val)==1) {
+ if (read_msr (cpu->number, MSR_IA32_THERM_CONTROL, &val) == 1) {
if (val & (1<<4)) {
printf(" Software-controlled clock: %f%% duty cycle\n",
((val >> 1) & 7) / 8.);
} else
printf(" Software-controlled clock disabled (full speed)\n");
}
- if (read_msr (cpu->number, MSR_IA32_THERM_STATUS, &val)==1) { /* THERM_STATUS */
+ if (read_msr (cpu->number, MSR_IA32_THERM_STATUS, &val) == 1) { /* THERM_STATUS */
printf(" Thermal status: ");
if (val & (1<<0))
printf("TooHot ");
@@ -82,5 +79,5 @@
printf("WasTooHot ");
printf("\n");
}
- printf ("\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/bluesmoke.c
^
|
| @@ -1,18 +1,16 @@
/*
- * $Id: bluesmoke.c,v 1.9 2003/04/11 00:17:20 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
- * Dump MCA registers.
- *
+ * Dump machine check registers.
*/
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include "../x86info.h"
+#include "Intel.h"
#define MCG_CAP 0x0179
#define MCG_CTL_PBIT 8
@@ -25,8 +23,6 @@
#define MC_STATUS 0x0401
#define MC_ADDR 0x402
-#define PENTIUM4(family) (family == 0xf)
-
void decode_Intel_bluesmoke(int cpunum, int family)
{
unsigned long long val, val2;
@@ -40,83 +36,83 @@
banks = val & 0xff;
- printf ("\nNumber of reporting banks : %d\n\n", banks);
+ printf("\nNumber of reporting banks : %d\n\n", banks);
- if (PENTIUM4(family)) {
+ if (family == 0xf) {
if ((val & (1<<MCG_EXT_PBIT))) {
extcount = (val >> 16) & 0xff;
- printf ("Number of extended MC registers : %d\n\n", extcount);
+ printf("Number of extended MC registers : %d\n\n", extcount);
}
else
- printf ("Erk, MCG_EXT not present! :%016llx:\n", val);
+ printf("Erk, MCG_EXT not present! :%016llx:\n", val);
}
else
if ((val & (1<<MCG_CTL_PBIT)) == 0)
- printf ("Erk, MCG_CTL not present! :%016llx:\n", val);
+ printf("Erk, MCG_CTL not present! :%016llx:\n", val);
if (read_msr(cpunum, MCG_CTL, &val) == 1) {
- printf ("MCG_CTL:\n");
+ printf("MCG_CTL:\n");
- printf (" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
+ printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
if ((val & (1<<0)) == 1) {
if (read_msr(cpunum, MC_CTL, &val2) == 1) {
- printf (" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf (" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf (" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf (" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf (" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf (" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
}
}
- printf (" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
+ printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
if (((val & (1<<1)) == 2) && (banks>1)) {
if (read_msr(cpunum, MC_CTL+4, &val2) == 1) {
- printf (" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf (" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf (" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf (" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf (" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf (" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
- printf (" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
- printf (" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
- printf (" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
+ printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
+ printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
}
}
- printf (" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
+ printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
if ((val & (1<<2)) == 4 && (banks>2)) {
if (read_msr(cpunum, MC_CTL+8, &val2) == 1) {
- printf (" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf (" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf (" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf (" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf (" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf (" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
}
}
- printf (" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
+ printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
if ((val & (1<<3)) == 8 && (banks>3)) {
if (read_msr(cpunum, MC_CTL+12, &val2) == 1) {
- printf (" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf (" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
}
}
}
- printf ("\n");
+ printf("\n");
for (i=0; i<banks; i++) {
- printf ("Bank: %d (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
- printf ("MC%dCTL: ", i);
+ printf("Bank: %d (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
+ printf("MC%dCTL: ", i);
dumpmsr_bin (cpunum, MC_CTL+i*4, 64);
- printf ("MC%dSTATUS: ", i);
+ printf("MC%dSTATUS: ", i);
dumpmsr_bin (cpunum, MC_STATUS+i*4, 64);
- printf ("MC%dADDR: ", i);
+ printf("MC%dADDR: ", i);
dumpmsr_bin (cpunum, MC_ADDR+i*4, 64);
- printf ("\n");
+ printf("\n");
}
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/cachesize.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: cachesize.c,v 1.14 2005/08/07 18:42:37 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -10,7 +8,6 @@
* References:
* http://developer.intel.com/
* http://microcodes.sourceforge.net/CPUID.htm
- *
*/
#include <stdio.h>
@@ -36,19 +33,21 @@
static struct _cache_table L1I_cache_table[] =
{
- { 0x6, 8, "L1 Instruction cache: 8KB, 4-way associative. 32 byte line size." },
+ { 0x6, 8, "L1 Instruction cache: 8KB, 4-way associative. 32 byte line size." },
{ 0x8, 16, "L1 Instruction cache: 16KB, 4-way associative. 32 byte line size." },
- { 0x30, 32, "L1 Instruction cache: 32KB, 8-way associative. 64 byte line size." },
+ { 0x9, 32, "L1 Instruction cache: 32KB, 4-way associative. 64 byte line size." },
+ { 0x30, 32, "L1 Instruction cache: 32KB, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L1D_cache_table[] =
{
- { 0xa, 8, "L1 Data cache: 8KB, 2-way associative. 32 byte line size." },
+ { 0xa, 8, "L1 Data cache: 8KB, 2-way associative. 32 byte line size." },
{ 0xc, 16, "L1 Data cache: 16KB, 4-way associative. 32 byte line size." },
+ { 0xd, 16, "L1 Data cache: 16KB, 4-way associative. 64 byte line size. ECC." },
{ 0x2c, 32, "L1 Data cache: 32KB, 8-way associative. 64 byte line size." },
{ 0x60, 16, "L1 Data cache: 16KB, sectored, 8-way associative. 64 byte line size." },
- { 0x66, 8, "L1 Data cache: 8KB, sectored, 4-way associative. 64 byte line size." },
+ { 0x66 , 8, "L1 Data cache: 8KB, sectored, 4-way associative. 64 byte line size." },
{ 0x67, 16, "L1 Data cache: 16KB, sectored, 4-way associative. 64 byte line size." },
{ 0x68, 32, "L1 Data cache: 32KB, sectored, 4-way associative. 64 byte line size." },
{ 0, 0, NULL }
@@ -56,86 +55,103 @@
static struct _cache_table L2_cache_table[] =
{
- { 0x39, 128, "L2 unified cache: 128KB, 4-way associative. 64 byte line size." },
- { 0x3a, 192, "L2 unified cache: 192KB, 6-way associative. 64 byte line size." },
- { 0x3b, 128, "L2 unified cache: 128KB, 2-way associative. 64 byte line size." },
- { 0x3c, 256, "L2 unified cache: 256KB, 4-way associative. 64 byte line size." },
- { 0x3d, 384, "L2 unified cache: 384KB, 6-way associative. 64 byte line size." },
- { 0x3e, 512, "L2 unified cache: 512KB, 4-way associative. 64 byte line size." },
- { 0x41, 128, "L2 unified cache: 128KB, 4-way associative. 32 byte line size." },
- { 0x42, 256, "L2 unified cache: 256KB, 4-way associative. 32 byte line size." },
- { 0x43, 512, "L2 unified cache: 512KB, 4-way associative. 32 byte line size." },
- { 0x44, 1024, "L2 unified cache: 1MB, 4-way associative. 32 byte line size." },
- { 0x45, 2048, "L2 unified cache: 2MB, 4-way associative. 32 byte line size." },
- { 0x79, 128, "L2 unified cache: 128KB, sectored, 8-way associative. 64 byte line size." },
- { 0x7a, 256, "L2 unified cache: 256KB, sectored, 8-way associative. 64 byte line size." },
- { 0x7b, 512, "L2 unified cache: 512KB, sectored, 8-way associative. 64 byte line size." },
- { 0x7c, 1024, "L2 unified cache: 1MB, sectored, 8-way associative. 64 byte line size." },
- { 0x7d, 2048, "L2 unified cache: 2MB, sectored, 8-way associative. 64 byte line size." },
- { 0x7f, 512, "L2 unified cache: 512KB, 2-way associative. 64 byte line size." },
- { 0x82, 256, "L2 unified cache: 256KB, 8-way associative. 32 byte line size." },
- { 0x83, 512, "L2 unified cache: 512KB, 8-way associative. 32 byte line size." },
- { 0x84, 1024, "L2 unified cache: 1MB, 8-way associative. 32 byte line size." },
- { 0x85, 2048, "L2 unified cache: 2MB, 8-way associative. 32 byte line size." },
- { 0x86, 512, "L2 unified cache: 512KB, 4-way associative. 64 byte line size." },
- { 0x87, 1024, "L2 unified cache: 1MB, 8-way associative. 64 byte line size." },
+ { 0x21, 256, "L2 (MLC): 256KB, 8-way associative. 64 byte line size." },
+ { 0x39, 128, "L2 cache: 128KB, 4-way associative. Sectored. 64 byte line size." },
+ { 0x3a, 192, "L2 cache: 192KB, 6-way associative. Sectored. 64 byte line size." },
+ { 0x3b, 128, "L2 cache: 128KB, 2-way associative. Sectored. 64 byte line size." },
+ { 0x3c, 256, "L2 cache: 256KB, 4-way associative. Sectored. 64 byte line size." },
+ { 0x3d, 384, "L2 cache: 384KB, 6-way associative. Sectored. 64 byte line size." },
+ { 0x3e, 512, "L2 cache: 512KB, 4-way associative. Sectored. 64 byte line size." },
+/* { 0x3f, 256, "L2 cache: 256KB, 2-way associative. Sectored. 64 byte line size." }, */
+/* 3f is no longer listed. */
+ { 0x41, 128, "L2 cache: 128KB, 4-way associative. 32 byte line size." },
+ { 0x42, 256, "L2 cache: 256KB, 4-way associative. 32 byte line size." },
+ { 0x43, 512, "L2 cache: 512KB, 4-way associative. 32 byte line size." },
+ { 0x44, 1024, "L2 cache: 1MB, 4-way associative. 32 byte line size." },
+ { 0x45, 2048, "L2 cache: 2MB, 4-way associative. 32 byte line size." },
+ { 0x48, 3072, "L2 cache: 3MB, 12-way associative. 64 byte line size. Unified on-die." },
+ { 0x4e, 6144, "L2 cache: 6MB, 24-way set associative, 64-byte line size." },
+ { 0x79, 128, "L2 cache: 128KB, sectored, 8-way associative. 64 byte line size." },
+ { 0x7a, 256, "L2 cache: 256KB, sectored, 8-way associative. 64 byte line size." },
+ { 0x7b, 512, "L2 cache: 512KB, sectored, 8-way associative. 64 byte line size." },
+ { 0x7c, 1024, "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0x7d, 2048, "L2 cache: 2MB, 8-way associative. 64 byte line size." },
+ { 0x7f, 512, "L2 cache: 512KB, 2-way associative. 64 byte line size." },
+ { 0x82, 256, "L2 cache: 256KB, 8-way associative. 32 byte line size." },
+ { 0x83, 512, "L2 cache: 512KB, 8-way associative. 32 byte line size." },
+ { 0x84, 1024, "L2 cache: 1MB, 8-way associative. 32 byte line size." },
+ { 0x85, 2048, "L2 cache: 2MB, 8-way associative. 32 byte line size." },
+ { 0x86, 512, "L2 cache: 512KB, 4-way associative. 64 byte line size." },
+ { 0x87, 1024, "L2 cache: 1MB, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L2L3_cache_table[] =
{
- { 0x46, 4096, "L2 unified cache: 4MB, 4-way associative. 64 byte line size." },
- { 0x47, 8192, "L2 unified cache: 8MB, 8-way associative. 64 byte line size." },
- { 0x49, 4096, "L2 unified cache: 4MB, 16-way associative. 64 byte line size." },
- { 0x4a, 6144, "L2 unified cache: 6MB, 12-way associative. 64 byte line size." },
- { 0x4b, 8192, "L2 unified cache: 8MB, 16-way associative. 64 byte line size." },
- { 0x4c, 12288, "L2 unified cache: 12MB, 12-way associative. 64 byte line size." },
- { 0x4d, 16384, "L2 unified cache: 16MB, 16-way associative. 64 byte line size." },
- { 0x78, 1024, "L2 unified cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0x46, 4096, "L2 cache: 4MB, 4-way associative. 64 byte line size." },
+ { 0x47, 8192, "L2 cache: 8MB, 8-way associative. 64 byte line size." },
+ { 0x49, 4096, "L2 cache: 4MB, 16-way associative. 64 byte line size." },
+ { 0x4a, 6144, "L2 cache: 6MB, 12-way associative. 64 byte line size." },
+ { 0x4b, 8192, "L2 cache: 8MB, 16-way associative. 64 byte line size." },
+ { 0x4c, 12288, "L2 cache: 12MB, 12-way associative. 64 byte line size." },
+ { 0x4d, 16384, "L2 cache: 16MB, 16-way associative. 64 byte line size." },
+ { 0x78, 1024, "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L3L2_cache_table[] =
{
- { 0x46, 4096, "L3 unified cache: 4MB, 4-way associative. 64 byte line size." },
- { 0x47, 8192, "L3 unified cache: 8MB, 8-way associative. 64 byte line size." },
- { 0x49, 4096, "L3 unified cache: 4MB, 16-way associative. 64 byte line size." },
- { 0x4a, 6144, "L3 unified cache: 6MB, 12-way associative. 64 byte line size." },
- { 0x4b, 8192, "L3 unified cache: 8MB, 16-way associative. 64 byte line size." },
- { 0x4c, 12288, "L3 unified cache: 12MB, 12-way associative. 64 byte line size." },
- { 0x4d, 16384, "L3 unified cache: 16MB, 16-way associative. 64 byte line size." },
- { 0x78, 1024, "L3 unified cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0x46, 4096, "L3 cache: 4MB, 4-way associative. 64 byte line size." },
+ { 0x47, 8192, "L3 cache: 8MB, 8-way associative. 64 byte line size." },
+ { 0x49, 4096, "L3 cache: 4MB, 16-way associative. 64 byte line size." },
+ { 0x4a, 6144, "L3 cache: 6MB, 12-way associative. 64 byte line size." },
+ { 0x4b, 8192, "L3 cache: 8MB, 16-way associative. 64 byte line size." },
+ { 0x4c, 12288, "L3 cache: 12MB, 12-way associative. 64 byte line size." },
+ { 0x4d, 16384, "L3 cache: 16MB, 16-way associative. 64 byte line size." },
+ { 0x78, 1024, "L3 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0xd0, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." },
+ { 0xd1, 1024, "L3 cache: 1MB, 4-way associative. 64 byte line size." },
+ { 0xd2, 2048, "L3 cache: 2MB, 4-way associative. 64 byte line size." },
+ { 0xd6, 1024, "L3 cache: 1MB, 8-way associative. 64 byte line size." },
+ { 0xd7, 2048, "L3 cache: 2MB, 8-way associative. 64 byte line size." },
+ { 0xd8, 4096, "L3 cache: 4MB, 8-way associative. 64 byte line size." },
+ { 0xdc, 2048, "L3 cache: 2MB, 12-way associative. 64 byte line size." },
+ { 0xdd, 4096, "L3 cache: 4MB, 12-way associative. 64 byte line size." },
+ { 0xe2, 2048, "L3 cache: 2MB, 16-way associative. 64 byte line size." },
+ { 0xe3, 4096, "L3 cache: 4MB, 16-way associative. 64 byte line size." },
+ { 0xe4, 8192, "L3 cache: 8MB, 16-way associative. 64 byte line size." },
+ { 0xde, 8192, "L3 cache: 8MB, 12-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L3_cache_table[] =
{
- { 0x22, 512, "L3 unified cache: 512KB, 4-way associative. 64 byte line size." },
- { 0x23, 1024, "L3 unified cache: 1MB, 8-way associative. 64 byte line size." },
- { 0x25, 2048, "L3 unified cache: 2MB, 8-way associative. 64 byte line size." },
- { 0x29, 4096, "L3 unified cache: 4MB, 8-way associative. 64 byte line size." },
+ { 0x22, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." },
+ { 0x23, 1024, "L3 cache: 1MB, 8-way associative. 64 byte line size." },
+ { 0x25, 2048, "L3 cache: 2MB, 8-way associative. 64 byte line size." },
+ { 0x29, 4096, "L3 cache: 4MB, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table ITLB_cache_table[] =
{
- { 0x1, 32, "Instruction TLB: 4KB pages, 4-way associative, 32 entries" },
- { 0x2, 2, "Instruction TLB: 4MB pages, fully associative, 2 entries" },
- { 0x50, 64, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries." },
+ { 0x1, 32, "Instruction TLB: 4KB pages, 4-way associative, 32 entries" },
+ { 0x2, 2, "Instruction TLB: 4MB pages, fully associative, 2 entries" },
+ { 0x50, 64, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries." },
{ 0x51, 128, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries." },
{ 0x52, 256, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 256 entries." },
{ 0xb0, 128, "Instruction TLB: 4K pages, 4-way associative, 128 entries." },
- { 0xb1, 4, "Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative" },
+ { 0xb1, 4, "Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative" },
{ 0, 0, NULL }
};
static struct _cache_table DTLB_cache_table[] =
{
- { 0x3, 64, "Data TLB: 4KB pages, 4-way associative, 64 entries" },
- { 0x4, 8, "Data TLB: 4MB pages, 4-way associative, 8 entries" },
- { 0x5, 32, "Data TLB: 4MB pages, 4-way associative, 32 entries" },
- { 0x56, 16, "L0 Data TLB: 4MB pages, 4-way set associative, 16 entries" },
- { 0x57, 16, "L0 Data TLB: 4MB pages, 4-way set associative, 16 entries" },
- { 0x5b, 64, "Data TLB: 4KB or 4MB pages, fully associative, 64 entries." },
+ { 0x3, 64, "Data TLB: 4KB pages, 4-way associative, 64 entries" },
+ { 0x4, 8, "Data TLB: 4MB pages, 4-way associative, 8 entries" },
+ { 0x5, 32, "Data TLB: 4MB pages, 4-way associative, 32 entries" },
+ { 0x56, 16, "L1 Data TLB: 4MB pages, 4-way set associative, 16 entries" },
+ { 0x57, 16, "L1 Data TLB: 4KB pages, 4-way set associative, 16 entries" },
+ { 0x5b, 64, "Data TLB: 4KB or 4MB pages, fully associative, 64 entries." },
{ 0x5c, 128, "Data TLB: 4KB or 4MB pages, fully associative, 128 entries." },
{ 0x5d, 256, "Data TLB: 4KB or 4MB pages, fully associative, 256 entries." },
{ 0xb3, 128, "Data TLB: 4K pages, 4-way associative, 128 entries." },
@@ -157,8 +173,8 @@
static void decode_Intel_cache(int des, struct cpudata *cpu, int output,
struct _cache_table *table)
{
- int k=0;
- int found=0;
+ int k = 0;
+ int found = 0;
/* "No 2nd-level cache or, if processor contains a valid 2nd-level
cache, no 3rd-level cache". Skip this pointless entry.*/
@@ -167,7 +183,7 @@
//TODO: Add description to link-list in cpu->
- while ((table[k].descriptor != 0) && (found==0)) {
+ while ((table[k].descriptor != 0) && (found == 0)) {
if (table[k].descriptor == des) {
if (table == TRACE_cache_table)
@@ -190,14 +206,14 @@
cpu->cachesize_L3 += table[k].size;
if (output)
- printf (" %s\n", table[k].string);
+ printf(" %s\n", table[k].string);
found = 1;
}
k++;
}
- if ((found==0) && (unknown_array[des]==0)) {
- unknown_array[des]=1;
+ if ((found == 0) && (unknown_array[des] == 0)) {
+ unknown_array[des] = 1;
found_unknown++;
}
}
@@ -205,7 +221,7 @@
static void decode_cache(struct cpudata *cpu, struct _cache_table *table, int output)
{
unsigned int i, j, n;
- unsigned long regs[4];
+ unsigned int regs[4];
/* Decode TLB and cache info */
cpuid(cpu->number, 2, ®s[0], ®s[1], ®s[2], ®s[3]);
@@ -230,15 +246,15 @@
}
}
-void clean_unknowns(struct _cache_table *table)
+static void clean_unknowns(struct _cache_table *table)
{
int j=0;
int des;
while (table[j].descriptor != 0) {
des = table[j++].descriptor;
- if (unknown_array[des]==1) {
- unknown_array[des]=0;
+ if (unknown_array[des] == 1) {
+ unknown_array[des] = 0;
found_unknown--;
}
}
@@ -264,11 +280,10 @@
oldknown = found_unknown;
decode_cache(cpu, L2_cache_table, output);
if (found_unknown > 0) {
- if (oldknown == found_unknown) {
+ if (oldknown == found_unknown)
decode_cache(cpu, L2L3_cache_table, output);
- } else {
+ else
decode_cache(cpu, L3L2_cache_table, output);
- }
}
decode_cache(cpu, L3_cache_table, output);
@@ -296,15 +311,15 @@
return;
if (output)
- printf ("Found unknown cache descriptors: ");
+ printf("Found unknown cache descriptors: ");
for (i=0; i<256; i++) {
- if (unknown_array[i]==1)
+ if (unknown_array[i] == 1)
if (output)
- printf ("%02x ", i);
+ printf("%02x ", i);
}
if (output)
- printf ("\n");
+ printf("\n");
found_unknown = 0;
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/eblcr.c
^
|
| @@ -1,3 +1,11 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Bus speed parsing.
+ */
+
#include <stdio.h>
#include "../x86info.h"
@@ -29,9 +37,9 @@
* 766MHz Celeron. 66MHz x 11.5 Being picked up as 133x5.0
* bus:1 mul:0
*/
-
-/* printf ("bus:%x mul:%x\n", bus, mul);*/
-
+
+/* printf("bus:%x mul:%x\n", bus, mul);*/
+
/* The mobile pIII added bit 27.
* This is zero on other intel and on the cyrix III */
@@ -40,11 +48,11 @@
busclock = buscode[1][bus]/100;
- if (busclock==0 || mult[mul]==0)
+ if (busclock == 0 || mult[mul] == 0)
printf("Unknown CPU/BUS multiplier (%d X %dMHz, %x).\n", mul, bus, lo);
cpuclk = (buscode[1][bus] * mult[mul])/200;
- printf ("Bus Speed (%dMHz) x Multiplier (%.1fx) = CPU speed %dMhz\n",
+ printf("Bus Speed (%dMHz) x Multiplier (%.1fx) = CPU speed %dMhz\n",
busclock,
(float) cpuclk/busclock,
cpuclk);
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Intel/identify-family15.c
^
|
| @@ -0,0 +1,344 @@
+/*
+ * (C) 2008 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Intel family 15 specific identification.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+static char p4_423_datasheet[]="http://developer.intel.com/design/pentium4/datashts/24919805.pdf";
+static char p4_478_datasheet[]="http://developer.intel.com/design/pentium4/datashts/24988703.pdf\n\thttp://developer.intel.com/design/pentium4/datashts/29864304.pdf";
+static char p4_errata[]="http://developer.intel.com/design/pentium4/specupdt/249199.htm";
+
+static char *intel_nameptr;
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+
+void Identify_Intel_family15(struct cpudata *cpu)
+{
+ intel_nameptr = cpu->name;
+
+ switch (model(cpu)) {
+ case 0x0: /* Family 15 */
+ cpu->connector = CONN_SOCKET_423;
+ cpu->datasheet_url = strdup(p4_423_datasheet);
+ cpu->errata_url = strdup(p4_errata);
+ add_to_cpuname("Pentium 4");
+ switch (cpu->stepping) {
+ case 7:
+ //SL4QD SL4SF = 1.3GHz
+ //SL4SG SL4SC = 1.4GHz
+ //SL4SH SL4TY = 1.5GHz
+ add_to_cpuname(" [B2]");
+ break;
+ case 0xA:
+ //SL5FW SL5GC 1.3GHz
+ //SL4WS SL4X2 SL59U SL5N7 1.4GHz
+ //SL4WT SL4X3 SL59V SL5NB 1.5GHz
+ //SL4WU SL4X4 SL5US SL5UW 1.6GHz
+ //SL57W SL57V SL59X SL5N9 1.7GHz
+ //SL4WV SL4X5 SL5UT SL5UV 1.8GHz
+ add_to_cpuname(" [C1]");
+ break;
+ }
+ break;
+
+ case 0x1:
+ cpu->connector = CONN_SOCKET_423;
+ add_to_cpuname("Pentium 4 (Willamette)");
+ cpu->datasheet_url = strdup(p4_423_datasheet);
+ cpu->errata_url = strdup(p4_errata);
+ switch (cpu->stepping) {
+ case 1:
+ //400FSB 256K L2
+ //SSpec MHz L3
+ //SL5G8 1.6 1M
+ //SL5S4 1.6 1M
+ //SL5FZ 1.4 512K
+ //SL5RZ 1.4 512K
+ //SL5G2 1.5 512K
+ //SL5RW 1.5 512K
+ add_to_cpuname(" [C0]");
+ break;
+ case 2:
+ //SL5TG SL5UE 1.4GHz
+ //SL5SX SL5TJ SL5UF SL62Y SL5TN 1.5GHz
+ //SL5VL SL5UL SL5VH SL5UJ 1.6GHz
+ //SL5SY SL5TK SL5UG SL62Z 1.7GHz
+ //SL5VM SL5VM SL5VJ SL5UK 1.8GHz
+ //SL5VN SL5WH SL5VK SL5WG 1.9GHz
+ //SL5SZ SL5TQ SL5TL 2GHz
+ add_to_cpuname(" [D0]");
+ break;
+ case 3:
+ //SL6BC SL679 1.6GHz
+ //SL6BD SL67A 1.7GHz
+ //SL6BE SL78B 1.8GHz
+ //SL6BF SL67C 1.9GHz
+ add_to_cpuname(" [E0]");
+ break;
+ }
+ break;
+ case 0x2:
+ cpu->connector = CONN_SOCKET_478;
+ cpu->datasheet_url = strdup(p4_478_datasheet);
+ cpu->errata_url = strdup(p4_errata);
+ switch (cpu->brand) {
+ case 15:
+ add_to_cpuname("Celeron (P4 core)");
+ break;
+ case 7:
+ default:
+ add_to_cpuname("Pentium 4 (Northwood)");
+ break;
+ }
+ switch (cpu->stepping) {
+ case 2:
+ //512K L2
+ // L3
+ //SL6GZ 1.5 1M
+ //SL6KB 1.5 1M
+ //SL6H2 1.9 2M
+ //SL6KC 1.9 2M
+ //SL66Z 2.0 1M
+ //SL6KD 2.0 1M
+ add_to_cpuname(" [A0]");
+ break;
+ case 4:
+ //SL66B 1.6GHz
+ //SL63X SL62P SL6BQ 1.8GHz
+ //SL6BR SL5YR 2GHz
+ //SL5YS SL6BS SL5ZU 2.2GHz
+ //SL6B3 SL67Y 2.26GHz (533MHz FSB)
+ //SL6BT SL65R SL67R 2.4GHz (400MHz FSB)
+ //SL6B4 SL67Z 2.4GHz (533MHz FSB)
+ //SL6B5 SL6B2 2.53GHz (533MHz FSB)
+ add_to_cpuname(" [B0]");
+ break;
+ case 5:
+ /*[M0] */
+ //SL6Z3 2.4GHz (800FSB)
+ //SL6Z5 2.8GHz (800FSB)
+ /* P4 Extreme edition.*/
+ //SL7AA 3.2GHz (800FSB) 2MB L3 cache
+ //SL7CH 3.4GHz (800FSB) 2MB L3 cache
+
+ /* 400FSB B1 512K L2 */
+ //SL6YJ 2.0 1M L3
+ //SL6Z6 2.0 1M L3
+ //SL6Z2 2.5 1M L3
+ //SL6Z7 2.5 1M L3
+ //SL6YL 2.8 2M L3
+ //SL6Z8 2.8 2M L3
+ add_to_cpuname(" [M0]");
+ break;
+ case 6:
+ //400FSB 512K L2
+ //SL79V 3.0 4M L3
+ //SL79Z 2.7 2M L3
+ //SL7A5 2.2 2M L3
+ add_to_cpuname(" [C0]");
+ break;
+ case 7:
+ //SL6HL SL6K6 2.8GHz (533MHz FSB)
+ //SL6LA SL6S6 1.8GHz
+ //SL6GQ SL6S7 SL6E7 2GHz
+ //SL6GR SL6SB SL6EB 2.2GHz
+ //SL6DU SL6RY SL6EE 2.26GHz (533FSB)
+ //SL6EF SL6DV SL6S9 SL6RZ SL6E9 2.4GHz (533FSB)
+ //SL6SA 2.5GHz (400FSB)
+ //SL6EG SL6S2 SL6DW 2.53GHz (533FSB)
+ //SL6SB 2.6GHz (400FSB)
+ //SL6S3 SL6SK 2.66GHz (533FSB)
+ //SL6S4 SL6SL 2.8GHz (533FSB)
+ //SL6S5 SL6K7 SL6SM SL6JJ 3.06GHz (533FSB)
+ add_to_cpuname(" [C1]");
+ break;
+ case 9:
+ //SL6QL 1.8GHz
+ //SL6QM SL6PK 2.0GHz
+ //SL6QN SL6PL 2.2GHz
+ //SL6QR SL6PB 2.26GHz (533FSB)
+ //SL6QP SL6PM 2.4GHz
+ //SL6QB SL6PC 2.4GHz (533FSB)
+ //SL6WF SL6WR 2.4GHz (800FSB)
+ //SL6QQ 2.5GHz
+ //SL6Q9 SL6PD 2.53GHz (533FSB)
+ //SL6QR 2.6GHz
+ //SL6WH SL6WS 2.6GHz (800FSB)
+ //SL6QA SL6PE 2.66GHz (533FSB)
+ //SL6QB SL6PF 2.8GHz (533FSB)
+ //SL6WJ SL6WT 2.8GHz (800FSB)
+ //SL6WU SL6WK 3GHz (800FSB)
+ //SL6QC SL6PG 3.06GHz (533FSB)
+ //SL6WG SL6WE 3.2GHz (800FSB)
+ //SL793 3.4GHz (800FSB)
+ add_to_cpuname(" [D1]");
+ break;
+ }
+ break;
+ case 0x3:
+ switch (cpu->stepping) {
+ case 3:
+ /*
+ sspec speed fsb l2 90nm
+ SL7D7 2.26GHz 533 512K
+ SL7FY 2.4GHz 800 1M
+ SL7E8 2.4GHz 533 1M
+ SL7E9 2.66GHz 533 1M
+ SL7D8 2.8GHz 533 1M
+ SL79K 2.8GHz 800 1M
+ SL79L 3.0GHz 800 1M
+ SL79M 3.2GHz 800 1M
+ SL7B8 3.2GHz 800 1M
+ SL7B9 3.4GHz 800 1M
+ SL7AJ 3.4GHz 800 1M
+
+ process = "0.09u";
+ 125 million transistors
+ 112mm2 die size
+ pipeline_stages=31
+ */
+ add_to_cpuname("Pentium 4 (Prescott) [C0]");
+ break;
+ case 4:
+ /*
+ 1M L2 90nm
+ sspec speed fsb
+ SL7E2 2.8GHz 533
+ SL7E3 2.8GHz 800
+ SL7KA 2.8GHz 800
+ SL7K9 2.8GHz 533
+ SL7E4 3.0GHz 800
+ SL7KB 3.0GHz 800
+ SL7L4 3.0GHz 800
+ SL7L5 3.2GHz 800
+ SL7E5 3.2GHz 800
+ SL7KC 3.2GHz 800
+ SL7E6 3.4GHz 800
+ SL7KD 3.4GHz 800
+ SL7YP 2.4GHz 533
+ SL7YU 2.66GHz 533
+ SL7J4 2.8GHz 533
+ SL7J5 2.8GHz 800
+ SL7KH 2.8GHz 533
+ SL7KJ 2.8GHz 800
+ SL7YV 2.93GHz 533
+ SL7J6 3.0GHz 800
+ SL7KK 3.0GHz 800
+ SL7J7 3.2GHz 800
+ SL7KL 3.2GHz 800
+ SL7LA 3.2GHz 800
+ SL7J8 3.4GHz 800
+ SL7KM 3.4GHz 800
+ SL7L8 3.4GHz 800
+ SL7J9 3.6GHz 800
+ SL7KN 3.6GHz 800
+ SL7L9 3.6GHz 800
+ */
+ add_to_cpuname("Pentium 4 (Prescott) [D0]");
+ break;
+ }
+ break;
+
+ case 0x4:
+ add_to_cpuname("Pentium 4 ");
+ switch (cpu->stepping) {
+ case 1:
+ /*
+ 1M L2 90nm
+ SL88F 2.4GHz 533
+ SL8B3 2.66GHz 533
+ SL88G 2.8GHz 533
+ SL88H 2.8GHz 800
+ SL7PL 2.8GHz 800
+ SL7PK 2.8GHz 533
+ SL7PM 3GHz 800
+ SL88J 3GHz 800
+ SL7PN 3.2GHz 800
+ SL88K 3.2GHz 800
+ SL88L 3.4GHz 800
+ SL7PP 3.4GHz 800
+ SL7PT 2.66GHz 533
+ SL82P 2.8GHz 800
+ SL7PR 2.8GHz 800
+ SL8HX 2.8GHz 800
+ SL85U 2.66GHz 533
+ SL8J8 2.66GHz 533
+ SL85V 2.93GHz 533
+ SL8J9 2.93GHz 533
+ SL87L 3.06GHz 533
+ SL8JA 3.06GHz 533
+ SL82X 3.0GHz 800
+ SL7PU 3.0GHz 800
+ SL8HZ 3.0GHz 800
+ SL7PW 3.2GHz 800
+ SL7PX 3.2GHz 800
+ SL82Z 3.2GHz 800
+ SL8J2 3.2GHz 800
+ SL7PY 3.4GHz 800
+ SL7PZ 3.4GHz 800
+ SL833 3.4GHz 800
+ SL7ZW 3.4GHz 800
+ SL8J5 3.4GHz 800
+ SL84X 3.6GHz 800
+ SL7Q2 3.6GHz 800
+ SL7NZ 3.6GHz 800
+ SL8J6 3.6GHz 800
+ SL82U 3.8GHz 800
+ SL84Y 3.8GHz 800
+ SL7P2 3.8GHz 800
+ SL8J7 3.8GHz 800
+ */
+ /*
+ 8MB L3 [C-0]
+ SL8EY 3.3GHz 667
+ SL8EW 3GHz 667
+ 4MB L3
+ SL8ED 2.8GHz 667
+ */
+ add_to_cpuname("(Prescott) [E0]");
+ break;
+ case 3:
+ /*
+ 2M L2 90nm
+ SL7Z9 3.0GHz 800
+ SL7Z8 3.2GHz 800
+ SL8Z7 3.4GHz 800
+ SL7Z5 3.6GHz 800
+ SL7Z4 3.73GHz 800
+ SL7Z3 3.8GHz 800
+ */
+ add_to_cpuname("(Prescott) [N0]");
+ break;
+ case 4:
+ /*
+ 1Mx2 L2 800MHz FSB
+ SL88T 2.8GHz
+ SL88S 3GHz
+ SL88R 3.2GHz
+ SL8FK 3.2GHz
+ */
+ add_to_cpuname("Extreme Edition [A0]");
+ break;
+ default:
+ add_to_cpuname("D (Foster)");
+ break;
+ }
+ break;
+
+ case 0x5:
+ cpu->connector = CONN_SOCKET_603;
+// cpu->datasheet_url = strdup(p4_478_datasheet);
+// cpu->errata_url = strdup(p4_errata);
+ add_to_cpuname("Pentium 4 Xeon (Foster)");
+ break;
+ default:
+ add_to_cpuname("Unknown CPU");
+ break;
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Intel/identify-family6-extended.c
^
|
| @@ -0,0 +1,269 @@
+/*
+ * (C) 2001,2008 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Intel family 6 specific decoding (Core family).
+ * All the CPUs described in this file have cpu->emodel set to 1
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+static char *intel_nameptr;
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+
+void Identify_Intel_family6core(struct cpudata *cpu)
+{
+ intel_nameptr = cpu->name;
+
+ switch (model(cpu)) {
+ case 7:
+ switch (cpu->stepping) {
+ case 6:
+ // sSpec step CoreFreq Bus cache
+ // SLAN3 C0 3.00 1333 12MB (2x6) QX9650
+ // SLANY C0 3.2 1600 12MB (2x6) QX9775
+/*
+sSpec name package step HFM/LFM/SLFM FSB IDAT L2Cache
+SLAQG T9300 m-FCPGA C-0 2.5/1.2/0.8 800 2.7 6
+SLAPV T9300 m-FCBGA C-0 2.5/1.2/0.8 800 2.7 6
+SLAPU T8300 m-FCBGA C-0 2.4/1.2/0.8 800 2.6 3
+SLAUU T8100 m-FCPGA C-0 2.1/1.2/0.8 800 2.3 3
+SLAPT T8100 m-FCBGA C-0 2.1/1.2/0.8 800 2.3 3
+SLAPT T8100 m-FCBGA C-0 2.1/1.2/0.8 800 2.3 3
+SLAPA T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3
+SLAPR T8300 m-FCBGA M-0 2.4/1.2/0.8 800 2.6 3
+SLAP9 T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAPS T8100 m-FCBGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAVJ T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAXG T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAZD T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAYZ T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAZC T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3
+SLAZB T9300 m-FCPGA C-0 2.5/1.2/0.8 800 2.7 6
+SLAYY T9300 m-FCPGA C-0 2.5/1.2/0.8 800 2.7 6
+SLAZA T9500 m-FCPGA C-0 2.6/1.2/0.8 800 2.8 6
+SLAYX T9500 m-FCPGA C-0 2.6/1.2/0.8 800 2.8 6
+SLAQJ X9000 m-FCPGA C-0 2.8/1.2/0.8 800 N/A 6
+SLAZ3 X9000 m-FCPGA C-0 2.8/1.2/0.8 800 N/A 6
+SLB47 T9600 m-FCPGA C-0 2.80/1.6/0.8 1066 2.93 6
+SLB43 T9600 m-FCBGA C-0 2.80/1.6/0.8 1066 2.93 6
+SLB46 T9400 m-FCPGA C-0 2.53/1.6/0.8 1066 2.66 6
+SL3BX T9400 m-FCBGA C-0 2.53/1.6/0.8 1066 2.66 6
+SLB4E P9500 m-FCPGA C-0 2.53/1.6/0.8 1066 2.66 6
+SL3BW P9500 m-FCBGA C-0 2.53/1.6/0.8 1066 2.66 6
+SLB3S P8600 m-FCPGA M-0 2.40/1.6/0.8 1066 2.53 3
+SLB4N P8600 m-FCBGA M-0 2.40/1.6/0.8 1066 2.53 3
+SLB3R P8400 m-FCPGA M-0 2.26/1.6/0.8 1066 2.40 3
+SLB4M P8400 m-FCBGA M-0 2.26/1.6/0.8 1066 2.40 3
+SLB3Q P8400 m-FCPGA M-0 2.26/1.6/0.8 1066 2.40 3
+SL3BV P8600 m-FCBGA C-0 2.40/1.6/0.8 1066 2.53 3
+SL3BU P8400 m-FCBGA C-0 2.26/1.6/0.8 1066 2.40 3
+SLB48 X9100 m-FCPGA C-0 3.06/1.6/0.8 1066 N/A 6
+SLAYS T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3
+SLAYU T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAYP T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3
+SLAYQ T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3
+SLG8E P7350 m-FCBGA C-0 2.00/1.6/0.8 1066 N/A 3
+SLB45 P7450 m-FCPGA C-0 2.13/1.6/0.8 1066 N/A 3
+SLB44 P7350 m-FCPGA C-0 2.00/1.6/0.8 1066 N/A 3
+SLB54 P7450 m-FCPGA M-0 2.13/1.6/0.8 1066 N/A 3
+SLB53 P7350 m-FCPGA M-0 2.00/1.6/0.8 1066 N/A 3
+SLB5J QX9300 m-FCPGA E-0 2.53/1.6/(n/a) 1066 2.8 45 12
+SLB5G Q9100 m-FCPGA E-0 2.26/1.6/(n/a) 1066 2.53 45 12
+SLB64 SP9400 m-FCBGA C-0 2.40/1.6/0.8 1066 2.53 25 6
+SLB63 SP9300 m-FCBGA C-0 2.26/1.6/0.8 1066 2.40 25 6
+SLB66 SL9400 m-FCBGA C-0 1.86/1.6/0.8 1066 2.13 17 6
+SLB65 SL9300 m-FCBGA C-0 1.60/0.8/0.8 1066 1.86 17 6
+SLB5V SU9400 m-FCBGA M-0 1.40/0.8/0.8 800 1.60 10 3
+SLB5Q SU9300 m-FCBGA M-0 1.20/0.8/0.8 800 1.40 10 3
+SLGAR SU3300 m-FCBGA M-0 1.20/0.8/(n/a) 800 N/A 5.5 3 (Celeron)
+SLGAS 723 m-FCBGA M-0 1.20/(n/a)/(n/a) 800 N/A 10 1 (Celeron)
+
+*/
+
+ add_to_cpuname("Core 2 quad ");
+ switch (cpu->MHz) {
+ case 3000: add_to_cpuname("Core 2 quad (QX9650) ");
+ break;
+ case 3200: add_to_cpuname("Core 2 Extreme quad (QX9775) ");
+ break;
+ }
+ add_to_cpuname("[C0] ");
+ break;
+ case 7:
+ // sSpec step CoreFreq Bus cache
+ // SLAWM C1 3.2 1600 12MB (2x6) QX9770
+ // SLAWQ C1 2.83 1600 12MB (2x6) Q9550
+ // SLAWR C1 2.66 1333 12MB (2x6) Q9450
+ // SLAWE M1 2.50 1333 6MB (2x3) Q9300
+ // SLB5M M1 2.33 1333 4MB (2x2) Q8200
+ add_to_cpuname("Core 2 quad ");
+ switch (cpu->MHz) {
+ case 3200: add_to_cpuname("(QX9770) [C1] ");
+ break;
+ case 2830: add_to_cpuname("(Q9550) [C1] ");
+ break;
+ case 2660: add_to_cpuname("(Q9450) [C1] ");
+ break;
+ case 2500: add_to_cpuname("(Q9300) [M1] ");
+ break;
+ case 2330: add_to_cpuname("(Q8200) [M1] ");
+ break;
+ }
+ break;
+ case 0xa:
+ // sSpec step CoreFreq Bus cache
+ // SLB8W E0 3.00 1333 12MB (2x6) Q9650
+ // SLB8V E0 2.83 1333 12MB (2x6) Q9550
+ // SLB6B R0 2.66 1333 6MB (2x3) Q9400
+ // SLB5W R0 2.5 1333 4MB (2x2) Q8300
+ add_to_cpuname("Core 2 quad ");
+ switch (cpu->MHz) {
+ case 3000: add_to_cpuname("(Q9650) [E0] ");
+ break;
+ case 2830: add_to_cpuname("(Q9550) [E0] ");
+ break;
+ case 2660: add_to_cpuname("(Q9400) [R0] ");
+ break;
+ case 2500: add_to_cpuname("(Q8300) [R0] ");
+ break;
+ }
+ break;
+ }
+ break;
+ case 0xa:
+ add_to_cpuname("Core i7 ");
+ //sSpec step CoreFreq/QuickpathGTs/DDR3 cache
+ //SLBCJ C-0 3.2/6.40/1066 8MB
+ //SLBCK C-0 2.93/4.80/1066 8MB
+ //SLBCH C-0 2.66/4.80/1066 8MB
+ break;
+ case 0xc:
+ add_to_cpuname("Atom ");
+ switch (cpu->stepping) {
+ case 1:
+ /*
+ * sSpec step TDP Name FSB EFMS HFM LFM Package MCU
+ * QDTD B0 2.5 x 533 106C1 1.6GHz 800MHz FCBGA8 M01106C1109
+ * QDTB B0 2.5 x 533 106C1 1.6GHz 800MHz FCBGA8 M01106C1109
+ * QGFD1 B0 X X 533 106C1 1.33GHz ---- FCBGA437 M01106C1109
+ */
+ break;
+ case 2:
+ /*
+ * sSpec step TDP Name FSB EFMS HFM LFM Package
+ *
+ *
+ * SLB6Q C0 0.65W Z500 400 106C2 0.8GHz 600Mhz FCBGA8
+ * SLB2C C0 2W Z510 400 106C2 1.1GHz 600Mhz FCBGA8
+ * SLB2H C0 2W Z520 533 106C2 1.33GHz 800Mhz FCBGA8
+ * SLB6P C0 2W Z530 533 106C2 1.60GHz 800Mhz FCBGA8
+ * QGZT C0 2.5W N270 533 106C2 1.60GHz 800MHz FCBGA8
+ * QKGY1 C0 8W 300 533 106C2 1.60GHz ------ FCBGA 437
+ * QGZR2 C0 4W 230 533 106C2 1.60GHz ----- FCBGA437 M01106C2208
+ * SLB2M C0 2.4W Z540 533 106C2 1.86GHz 800Mhz FCBGA8
+ */
+ switch (cpu->MHz) {
+ case 800: add_to_cpuname("Z500 [SLB6Q][C0]")
+ break;
+ case 1100: add_to_cpuname("Z510 [SLB2C][C0]")
+ break;
+ case 1330: add_to_cpuname("Z520 [SLB2H][C0]")
+ break;
+ case 1600: // could be a Z530,an N270,a QKGY1 or a QGZR2
+ break;
+ case 1860: add_to_cpuname("Z540 [SLB2M][C0]")
+ break;
+ }
+ break;
+ }
+ break;
+ case 0xe:
+ add_to_cpuname("Core ");
+ switch (cpu->stepping) {
+ case 8:
+ switch (cpu->MHz) {
+ case 1000:
+ // SL99W/SL8W7 533FSB
+ add_to_cpuname("Duo U2400/Solo U1300 [C-0]");
+ break;
+ case 1200:
+ // SL8W6 533FSB
+ add_to_cpuname("Solo U1400 [C-0]");
+ break;
+ case 1500:
+ // SL8VX 667FSB
+ add_to_cpuname("Duo L2300 [C-0]");
+ break;
+ case 1600:
+ // SL9JE/SL9JV/SL8VR/SL8VV/SL8VY/SL8W3/SL8VW 667FSB
+ add_to_cpuname("Solo T1300/Duo T2300(E)/Duo L2400");
+ break;
+ case 1800:
+ // SL92X/SL8VQ/SL8VU/SL92V/SL92X 667FSB
+ add_to_cpuname("Solo T1400/Duo T2400 [C-0]");
+ break;
+ case 2000:
+ // SL8VP/SL8VT/SL92U/SL92W 667FSB
+ add_to_cpuname("Solo T1500/Duo T2500 [C-0]");
+ break;
+ case 2150:
+ // SL8VN/SL8VS 667FSB
+ add_to_cpuname("Duo T2600 [C-0]");
+ break;
+ }
+ break;
+ case 0xc:
+ switch (cpu->MHz) {
+ case 1200:
+ // SL99V 533FSB
+ add_to_cpuname("Duo U2500 [D-0]");
+ break;
+ case 1800:
+ // SL9JU 667FSB
+ add_to_cpuname("Duo L2500 [D-0]");
+ break;
+ case 2300:
+ // SL9JP/SL9K4 667FSB
+ add_to_cpuname("Duo T2700 [D-0]");
+ break;
+ }
+ }
+ break;
+
+ case 23:
+ add_to_cpuname("Core 2 Duo ");
+ switch (cpu->stepping) {
+ case 4: add_to_cpuname("(Penryn)");
+ break;
+ case 6: add_to_cpuname("P8600");
+ break;
+ }
+ break;
+
+ case 26:
+ /*
+ * SLBCJ C-0 0x000106A4 3.20 / 6.40/ 1066 8MB
+ * SLBCK C-0 0x000106A4 2.93 / 4.80/ 1066 8MB
+ * SLBCH C-0 0x000106A4 2.66 / 4.80/ 1066 8MB
+ */
+ add_to_cpuname("Core i7 (Nehalem)");
+ switch (cpu->MHz) {
+ case 3200: add_to_cpuname(" [C-0][SLBCJ]");
+ break;
+ case 2930: add_to_cpuname(" [C-0][SLBCK]");
+ break;
+ case 2660: add_to_cpuname(" [C-0][SLBCH]");
+ break;
+ }
+ break;
+
+
+ default:
+ add_to_cpuname("Unknown model. ");
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Intel/identify-family6.c
^
|
| @@ -0,0 +1,619 @@
+/*
+ * (C) 2001,2008 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Intel family 6 specific decoding. (Pentium family)
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+static char *intel_nameptr;
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+
+void Identify_Intel_family6pentium(struct cpudata *cpu)
+{
+ intel_nameptr = cpu->name;
+
+ switch (model(cpu)) {
+ case 0x0:
+ add_to_cpuname("Pentium Pro A-Step");
+ cpu->connector = CONN_SOCKET_8;
+ break;
+ case 0x1:
+ add_to_cpuname("Pentium Pro");
+ cpu->connector = CONN_SOCKET_8;
+ switch (cpu->stepping) {
+ case 1:
+ add_to_cpuname(" [B0]");
+ switch (cpu->MHz) {
+ case 133:
+ //sSpec# Q0812, Q0815
+ break;
+ case 150:
+ //sSpec# Q0813, Q0816, SY002, SY011, SY014
+ break;
+ }
+ break;
+ case 2:
+ add_to_cpuname(" [C0]");
+ //sSpec# Q0822, Q0825, Q0826, SY010
+ break;
+ case 6:
+ add_to_cpuname(" [sA0]");
+ switch (cpu->MHz) {
+ case 166:
+ //sSpec# Q0864
+ break;
+ case 180:
+ //sSpec# SY012, Q0858, Q0860, Q0873, Q0910
+ break;
+ case 200:
+ //cache = 256 sSpec# SY013, Q0859, Q0874
+ //cache = 512 sSpec# Q0865
+ break;
+ }
+ break;
+ case 7:
+ add_to_cpuname(" [sA1]");
+ switch (cpu->MHz) {
+ case 166:
+ //sSpec# SY034, SY047, Q0918, Q0929, Q935
+ break;
+ case 180:
+ //sSpec# SY031, SY039, SU103, Q0871, Q0907
+ break;
+ case 200:
+ //cache = 256 sSpec# SY032, SY040, SL245, SL247, SU104, Q076, Q0872, Q0908, Q0909
+ //cache = 512 sSpec# SY048, Q0920, Q0924, Q932 , Q936
+ break;
+ }
+ break;
+ case 9:
+ add_to_cpuname(" [sB1]");
+ switch (cpu->MHz) {
+ case 166:
+ //sSpec# Q008, Q009, SL2FJ, SL22X
+ break;
+ case 180:
+ //sSpec# SL22S, SL22U, SL23L, Q033, Q035
+ break;
+ case 200:
+ //cache = 256 sSpec# L22T, SL22V, SL23M,SL254,SL255,Q034,Q036 ,Q083 ,Q084
+ //cache = 512 sSpec# Q010, Q011, SL22Z
+ //cache = 1MB sSpec# SL259, SL25A
+ break;
+ }
+ break;
+ }
+ break;
+ case 0x3:
+ add_to_cpuname("Pentium II ");
+ cpu->connector = CONN_SLOT_1;
+ switch (cpu->stepping) {
+ case 2:
+ add_to_cpuname("Overdrive [tdB0]");
+ break;
+ case 3:
+ add_to_cpuname("(Klamath) [C0]");
+ switch (cpu->MHz) {
+ case 233:
+ //sSpec# SL264, SL268, SL28K
+ break;
+ case 266:
+ //sSpec# SL265, SL269, SL28L
+ break;
+ case 300:
+ //sSpec# SL28R, SL2MZ
+ break;
+ }
+ break;
+ case 4:
+ add_to_cpuname("(Klamath) [C1]");
+ switch (cpu->MHz) {
+ case 233:
+ //sSpec# SL2HD, SL2HF, SL2QA
+ break;
+ case 266:
+ //sSpec# SL2HC, SL2HE, SL2QB
+ break;
+ case 300:
+ //sSpec# SL2HA, SL2QC
+ break;
+ }
+ break;
+ }
+ break;
+ case 0x4:
+ //Does this exist? Its not in Intels spec update.
+ cpu->connector = CONN_SLOT_1;
+ add_to_cpuname("Pentium II (Deschutes?)");
+ break;
+ case 0x5:
+ cpu->connector = CONN_SLOT_1;
+ switch (cpu->cachesize_L2) {
+ case 0:
+ add_to_cpuname("Celeron (Covington)");
+ break;
+
+ case 256:
+ add_to_cpuname("Mobile Pentium II (Dixon)");
+ break;
+
+ case 512:
+ switch (cpu->stepping) {
+ case 0:
+ add_to_cpuname("Pentium II [dA0]");
+ switch (cpu->MHz) {
+ case 266:
+ //sSpec# SL2K9
+ break;
+ case 333:
+ //sSpec# SL2KA, SL2QF
+ break;
+ }
+ break;
+ case 1:
+ add_to_cpuname("Pentium II (Deschutes) [dA1]");
+ switch (cpu->MHz) {
+ case 300:
+ //66 bus sSpec# SL35V, SL2VY
+ break;
+ case 333:
+ //66 bus sSpec# SL2QH, SL2S5, SL2ZP
+ break;
+ case 350:
+ //100Bus - sSpec# SL2ZQ, SL2S6, SL2SF
+ break;
+ case 400:
+ //100Bus - sSpec# Sl2S7, SL2SH
+ break;
+ }
+ break;
+ case 2:
+ add_to_cpuname("Pentium II (Deschutes) [dB0]");
+ switch (cpu->MHz) {
+ case 266:
+ //66Bus sSpec# SL33D, SL2W7
+ break;
+ case 300:
+ //66Bus - SL2YK, SL2W8
+ break;
+ case 333:
+ //66Bus - SL2KE, SL2TV
+ break;
+ case 350:
+ //100Bus - SL2WZ, SL2U3, SL2U4, SL356, SL37F, SL3FN
+ break;
+ case 400:
+ //100Bus - SL2YM, SL37G, SL2U5, SL2U6, SL357, SL3EE, SL3F9
+ break;
+ case 450:
+ //100Bus - SL2WB, SL37H, SL2U7, SL358
+ break;
+ }
+ break;
+ case 3:
+ add_to_cpuname("Pentium II (Deschutes) [dB1]");
+ switch (cpu->MHz) {
+ case 350:
+ //100Bus - SL38M, SL36U, SL3J2
+ break;
+ case 400:
+ //100Bus - SL38N, SL38Z, SL3D5
+ break;
+ }
+ break;
+ default:
+ add_to_cpuname("Pentium II");
+ break;
+ }
+ }
+ break;
+ case 0x6:
+ cpu->connector = CONN_SOCKET_370;
+ if (cpu->cachesize_L2 == 128) {
+ add_to_cpuname("Celeron (Mendocino)");
+ break;
+ }
+ switch (cpu->stepping) {
+ case 0:
+ add_to_cpuname("Celeron-A [mA0]");
+ break;
+ case 5:
+ add_to_cpuname("Celeron-A [mB0]");
+ break;
+ case 0xA:
+ add_to_cpuname("Mobile Pentium II [mdA0]");
+ break;
+ default:
+ add_to_cpuname("Celeron / Mobile Pentium II");
+ break;
+ }
+ break;
+ case 0x7:
+ cpu->connector = CONN_SLOT_1;
+ switch (cpu->stepping) {
+ case 2:
+ // Core=500 FSB=100
+ // SL2XU SL3C9 (l2=512)
+ // SL2XV SL3CA (l2=1MB)
+ // SL2XW SL3CB (l2=2MB)
+ add_to_cpuname("Pentium III (Katmai) [kB0]");
+ break;
+ case 3:
+ // Core=550 FSB=100
+ // SL3FK SL3D9 SL3AJ SL3Y4 SL3FR SL3LM (l2=512)
+ // SL3DA SL3CE SL3TW SL3LN (l2=1mb)
+ // SL3DB SL3CF SL3LP (l2=2mb)
+ //
+ // Core 500 FSB=100
+ // SL385 (l2=512)
+ // SL386 (l2=1MB)
+ // SL387 (l2=2MB)
+ add_to_cpuname("Pentium III (Katmai) [kC0]");
+ break;
+ default:
+ add_to_cpuname("Pentium III/Pentium III Xeon");
+ break;
+ }
+ decode_serial_number(cpu);
+ break;
+ case 0x8:
+ switch (cpu->brand) {
+ case 2:
+ add_to_cpuname("Pentium III/Pentium III-M (Coppermine)");
+ switch (cpu->stepping) {
+ case 1:
+ add_to_cpuname(" [cA2]");
+ break;
+ case 3:
+ add_to_cpuname(" [cB0]");
+ break;
+ case 6:
+ add_to_cpuname(" [cC0]");
+ break;
+ case 0xA:
+ add_to_cpuname(" [cD0]");
+ break;
+ }
+ break;
+ case 3:
+ add_to_cpuname("Pentium III Xeon");
+ switch (cpu->stepping) {
+ case 1:
+ // l2=256KB FSB=133
+ // Core=600 SL3BJ SL3BK SL3SS
+ // Core=667 SL3BL SL3DC SL3ST
+ // Core=733 SL3SF SL3SG SL3SU
+ // Core=800 SL3V2 SL3V3 SL3VU
+ add_to_cpuname(" [A2]");
+ break;
+ case 3:
+ // l2=256 FSB=133
+ // Core=600 SL3WM SL3WN
+ // Core=667 SL3WP SL3WQ
+ // Core=733 SL3WR SL3WS
+ // Core=800 SL3WT SL3WU
+ // Core=866 SL3WV SL3WW SL4PZ
+ // Core=933 SL3WX SL3WY
+ add_to_cpuname(" [B0]");
+ break;
+ case 6:
+ // l2=256 FSB=133
+ // Core=733 SL4H6 SL4H7
+ // Core=800 SL4H8 SL4H9
+ // Core=866 SL4HA SL4HB SL4U2
+ // Core=933 SL4HC SL4HD SL4R9
+ // Core=1000 SL4HE SL4HF
+ add_to_cpuname(" [C0]");
+ break;
+ }
+ break;
+
+ case 8:
+ // cpu->connector = CONN_BGA2; - Could also be Micro-PGA2
+ add_to_cpuname("Mobile Pentium III");
+ break;
+
+ default:
+ cpu->connector = CONN_SOCKET_370_FCPGA;
+ if (cpu->cachesize_L2 == 128) {
+ add_to_cpuname("Celeron");
+ } else {
+ add_to_cpuname("Pentium III");
+ }
+ add_to_cpuname(" (Coppermine)");
+ switch (cpu->stepping) {
+ case 1:
+ add_to_cpuname(" [cA2]");
+ break;
+ case 3:
+ add_to_cpuname(" [cB0]");
+ break;
+ case 6:
+ add_to_cpuname(" [cC0]");
+ break;
+ case 0xA:
+ add_to_cpuname(" [cD0]");
+ break;
+ }
+ break;
+ }
+ decode_serial_number(cpu);
+ break;
+
+ case 0x9:
+// cpu->connector =
+ add_to_cpuname("Pentium M (Banias)");
+ break;
+
+ case 0xa:
+ cpu->connector = CONN_SLOT_1;
+ switch (cpu->brand) {
+ case 0:
+ add_to_cpuname("Pentium II (Deschutes)");
+ break;
+ case 1:
+ add_to_cpuname("Celeron");
+ break;
+ case 2:
+ add_to_cpuname("Pentium III");
+ decode_serial_number(cpu);
+ break;
+ case 3:
+ // FSB=100
+ add_to_cpuname("Pentium III Xeon");
+ decode_serial_number(cpu);
+ switch (cpu->stepping) {
+ case 0:
+ // Core=700
+ // L2=1MB SL3U4 SL3U5 SL4GD SL4GE
+ // L2=2MB SL3WZ SL3X2 SL4GF SL4GG
+ add_to_cpuname(" [A0]");
+ break;
+ case 1:
+ // Core=700
+ // L2=1MB SL49P SL49Q SL4RZ
+ // L2=2MB SL49R SL49S SL4R3
+ add_to_cpuname(" [A1]");
+ break;
+ case 4:
+ // Core=700
+ // L2=1MB SL4XU SL5D4 SL4XV
+ // L2=2MB SL4XW SL5D5 SL4XX
+ // Core=900
+ // L2=2MB SL4XY SL4XZ SL5D3
+ add_to_cpuname(" [B0]");
+ break;
+ }
+ break;
+ case 4:
+ add_to_cpuname("Pentium III (Cascades)");
+ decode_serial_number(cpu);
+ break;
+ default:
+ add_to_cpuname("Unknown CPU");
+ break;
+ }
+ break;
+
+ case 0xb:
+ switch (cpu->brand) {
+ case 1:
+ case 3:
+ cpu->connector = CONN_SLOT_1;
+ add_to_cpuname("Celeron (Tualatin) [tA1/cA2]");
+ break;
+ case 6:
+ cpu->connector = CONN_MICROFCBGA;
+ add_to_cpuname("Pentium III-M");
+ decode_serial_number(cpu);
+ break;
+ default:
+ cpu->connector = CONN_SLOT_1;
+ switch (cpu->stepping) {
+ case 1:
+ add_to_cpuname("Pentium III (Tualatin) [tA1/cA2]");
+ break;
+ case 4:
+ add_to_cpuname("Pentium III [B-1]");
+ break;
+ default:
+ add_to_cpuname("Unknown CPU");
+ break;
+ }
+ decode_serial_number(cpu);
+ break;
+ }
+ break;
+
+ case 0xd:
+ add_to_cpuname("Pentium M ");
+ cpu->connector = CONN_MICROFCBGA;
+ switch (cpu->stepping) {
+ case 1: add_to_cpuname("(Dothan) [A-1]");
+ break;
+
+ case 2: add_to_cpuname("(Dothan) [A-2]");
+ break;
+
+ /*
+ S-spec Processor Hi-Freq Low-Freq
+ Number
+ SL7EM 755 2.0GHz 600MHz
+ SL7EL 755 2.0GHz 600MHz
+ SL7EN 745 1.8GHz 600MHz
+ SL7EQ 745 1.8GHz 600MHz
+ SL7EP 735 1.7GHz 600MHz
+ SL7ER 735 1.7GHz 600MHz
+ SL7EG 725 1.6GHz 600MHz
+ SL7F2 725 1.6GHz 600MHz
+ SL7GL 715 1.5GHz 600MHz
+ SL7GK 715 1.5GHz 600MHz
+ SL7VC 738 1.4GHz 600MHz
+ SL7F4 733 1.1GHz 600MHz
+ SL7VD 733 1.1GHz 600MHz
+ SL7V2 723 1.0GHz 600MHz
+ */
+ case 6: add_to_cpuname("(Dothan) [B-1]");
+ break;
+
+ /*
+ FSB=533 2MB L2 90nm
+ SL86G 730 1.6GHz 800MHz
+ SL7SA 740 1.73GHz 800MHz
+ SL7S9 750 1.86GHz 800MHz
+ SL7SM 760 2.0GHz 800MHz
+ SL7SL 770 2.13GHz 800MHz
+ SL7VB 780 2.26GHz 800MHz
+ SL86M 730 1.6GHz 800MHz
+ SL7S8 740 1.73GHz 800MHz
+ SL7SR 750 1.86GHz 800MHz
+ Sl7SQ 760 2.0GHz 800MHz
+ SL7SP 770 2.13GHz 800MHz
+ SL7SN 780 2.26GHz 800MHz
+ SL86B 740 1.73GHz 800MHz
+ SL86A 750 1.86GHz 800MHz
+ SL869 760 2.0GHz 800MHz
+ SL868 770 2.13GHz 800MHz
+ SL8QK 780 2.26GHz 800MHz
+ FSB=400
+ SL8QF 778 1.6GHz 600MHz
+ SL89X 758 1.5GHz 600MHz
+ SL8A3 723 1.0GHz 600MHz
+ SL8LM 733J 1.1GHz 600MHz
+ SL8A2 733J 1.1GHz 600MHz
+ SL89Z 753 1.2GHz 600MHz
+ SL8LL 753 1.2GHz 600MHz
+ SL8QG 778 1.6GHz 600MHz
+ SL89M 758 1.5GHz 600MHz
+ SL89R 723 1.0GHz 600MHz
+ SL8LT 733J 1.1GHz 600MHz
+ SL89Q 733J 1.1GHz 600MHz
+ SL89P 753 1.2GHz 600MHz
+ SL8LS 753 1.2GHz 600MHz
+ SL89N 738 1.4GHz 600MHz
+ SL89Y 738 1.4GHz 600MHz
+ */
+ case 8: add_to_cpuname("(Dothan) [C-0]");
+ break;
+ }
+ break;
+ /*
+ * ARGH. Intel made some Core CPUs without setting the efamily or emodel to 1.
+ */
+ case 0xf:
+ add_to_cpuname("Core 2 ");
+ switch (cpu->stepping) {
+ case 2:
+ /*
+ * 2M Level2 cache
+ * SL9TB L2 E4300 1.8GHz/800Mhz
+ * SLA3F L2 E4400 2GHz/800MHz
+ * SL9TA L2 E6300 1.86GHz/1066MHz
+ * SL9T9 L2 E6400 2.13GHz/1066MHz
+ */
+ add_to_cpuname("Duo [L2]");
+ break;
+ case 5:
+ add_to_cpuname("Duo ");
+ break;
+ case 6:
+ /*
+ * 2MB L2 cache
+ * - SL9SA B2 E6300 1.86GHz/1066MHz
+ * - SL9S9 B2 E6400 2.13GHz/1066MHz
+ * 4MB L2 cache
+ * - SLA4U B2 E6320 1.86GHz/1066MHz
+ * - SLA4T B2 E6420 2.13GHz/1066MHz
+ * - SL9S8 B2 E6600 2.4GHz/1066MHz
+ * - SL9ZL B2 E6600 2.4GHz/1066MHz
+ * - SL9S7 B2 E6700 2.66GHz/1066MHz
+ * - SL9ZF B2 E6700 2.66GHz/1066MHz
+ * - SLAA5 G0 E6540 2.33GHz/1.333MHz
+ * - SLA9X G0 E6550 2.33GHz/1.333MHz
+ * - SLA9V G0 E6750 2.66GHz/1.333MHz
+ * - SLA9U G0 E6850 3GHz/1.333MHz
+ * - SL9S5 B2 X6800 2.93GHz/1066MHz
+ */
+ add_to_cpuname("Duo ");
+ switch (cpu->cachesize_L2) {
+ case 2048:
+ add_to_cpuname("[B2]");
+ if (cpu->MHz/100 == 1860)
+ add_to_cpuname("[SL9SA] E6300");
+ if (cpu->MHz/100 == 2130)
+ add_to_cpuname("[SL9S9] E6400");
+ break;
+ case 4096:
+ break;
+ }
+ break;
+ case 7:
+ /*
+ * All quad-core.
+ * SL9UK B3 8MB QX6800 2.93GHz/1066MHz
+ * SL9UL B3 8MB QX6700 2.66GHz/1066MHz
+ * SL9UM B3 8MB QX6600 2.4GHz/1066MHz
+ * SLACP G0 8MB QX6800 2.93GHz/1066MHz
+ */
+ add_to_cpuname("Quad (Kentsfield) ");
+ switch (cpu->MHz) {
+ case 2930: add_to_cpuname("[SL9UK/SLACP] [B3/G0] QX6800");
+ break;
+ case 2660: add_to_cpuname("[SL9UL] [B3] QX6700");
+ break;
+ case 2400: add_to_cpuname("[SL9UM] [B3] QX6600");
+ break;
+ }
+ break;
+
+ case 0xa:
+ /* sCode Procname (IDA/HFM)
+ * SLA43 T7700 (2.6GHz/2.4GHz)
+ * SLA3M T7700 (2.6GHz/2.4GHz)
+ * SLA44 T7500 (2.4GHz/2.2GHz)
+ * SLA3N T7500 (2.4GHz/2.2GHz)
+ * SLA45 T7300 (2.4GHz/2.0GHz)
+ * SLA3P T7300 (2.2GHz/2.0GHz)
+ * SLA3R L7500 (1.8GHz/1.6GHz)
+ * SLA3S L7300 (1.6GHz/1.4GHz)
+ * SLA33 X7900 (2.8GHz)
+ * SLA6Z X7800 (2.6GHz)
+ */
+ add_to_cpuname(" [E1]");
+ break;
+
+ case 0xb:
+ /*
+ * SLALT G0 2M E4700 2.6GHz/800MHz
+ *
+ * SLAFN G0 8M QX6850 3GHz/1333MHz
+ * SLACQ G0 8M Q6700 2.66GHz/1066MHz
+ * SLACR G0 8M Q6600 2.4GHz/1066MHz
+ */
+ if (cpu->cachesize_L2 == 2048) {
+ add_to_cpuname("Duo [G0]");
+ } else
+ add_to_cpuname("Quad ");
+ break;
+
+ case 0xd:
+ /*
+ * SLA98 M0 2M E4400 2GHz/800MHz
+ * SLA95 M0 2M E4500 2.2GHz/800MHz
+ * SLA94 M0 2M E4600 2.4GHz/800MHz
+ */
+ add_to_cpuname("Duo [M0]");
+ break;
+ }
+ break;
+
+ default:
+ add_to_cpuname("Unknown model. ");
+ }
+}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/identify.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: identify.c,v 1.60 2004/08/20 13:05:56 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -10,7 +8,6 @@
* References:
* http://developer.intel.com/
* http://microcodes.sourceforge.net/CPUID.htm
- *
*/
#include <stdio.h>
@@ -21,1118 +18,126 @@
static char *intel_nameptr;
#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
-static char p4_423_datasheet[]="http://developer.intel.com/design/pentium4/datashts/24919805.pdf";
-static char p4_478_datasheet[]="http://developer.intel.com/design/pentium4/datashts/24988703.pdf\n\thttp://developer.intel.com/design/pentium4/datashts/29864304.pdf";
-static char p4_errata[]="http://developer.intel.com/design/pentium4/specupdt/249199.htm";
-
-
-void Identify_Intel (struct cpudata *cpu)
+void Identify_Intel(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
- int reserved;
+ unsigned int eax, ebx, ecx, edx;
- cpu->vendor = VENDOR_INTEL;
intel_nameptr = cpu->name;
- if (cpu->maxi < 1)
- return;
-
- /* Family/model/type etc */
- cpuid (cpu->number, 1, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
+ cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
+ cpu->emodel = (eax >> 16) & 0xf;
+ cpu->efamily= (eax >> 20) & 0xff;
cpu->type = (eax >> 12) & 0x3;
- cpu->brand = (ebx & 0xf);
- reserved = eax >> 14;
+
+ cpu->brand = ebx & 0xf;
+ cpu->apicid = ebx >> 24;
+ cpu->nr_logical = (ebx >> 16) & 0xff;
cpu->flags_ecx = ecx; // Used for identification of Core 2
cpu->flags_edx = edx;
+ /* Figure out number of cores on this package. */
+ cpu->nr_cores = 1;
+ if (cpu->maxi >= 4) {
+ cpuid4(cpu->number, 0, &eax, &ebx, &ecx, &edx);
+ if (eax & 0x1f)
+ cpu->nr_cores = ((eax >> 26) + 1);
+ }
+
decode_Intel_caches(cpu, 0);
switch (cpu->family) {
case 4: add_to_cpuname("i486 ");
- break;
- case 5: add_to_cpuname("Pentium ");
- break;
- }
-
- switch (tuple(cpu) & 0xff0) {
- case 0x400: /* Family 4 */
- add_to_cpuname("DX-25/33");
- break;
- case 0x410:
- add_to_cpuname("DX-50");
- break;
- case 0x420:
- add_to_cpuname("SX");
- break;
- case 0x430:
- add_to_cpuname("487/DX2");
- break;
- case 0x440:
- add_to_cpuname("SL");
- break;
- case 0x450:
- add_to_cpuname("SX2");
- break;
- case 0x470:
- add_to_cpuname("write-back enhanced DX2");
- break;
- case 0x480:
- add_to_cpuname("DX4");
- cpu->connector = CONN_SOCKET_3;
- //transistors = 1600000;
- //fab_process = "0.6 micron CMOS";
- //die_size = "345 sq. mm";
- //introduction_date = "March 1994";
- break;
- case 0x490:
- add_to_cpuname("write-back enhanced DX4");
- cpu->connector = CONN_SOCKET_3;
- break;
-
- case 0x500:
- add_to_cpuname("A-step");
- cpu->connector = CONN_SOCKET_4;
- break;
- case 0x510:
- add_to_cpuname("60/66");
- cpu->connector = CONN_SOCKET_4;
- break;
- case 0x520:
- add_to_cpuname("75-200");
- cpu->connector = CONN_SOCKET_5_7;
- break;
- case 0x530:
- add_to_cpuname("Overdrive");
- cpu->connector = CONN_SOCKET_4;
- break;
- case 0x540:
- add_to_cpuname("MMX");
- cpu->connector = CONN_SOCKET_7;
- //transistors = 4500000;
- //fab_process = "0.35 micron CMOS";
- //die_size = "140 sq.mm";
- //introduction_date = "June 1997";
- break;
- case 0x570:
- add_to_cpuname("Mobile");
- cpu->connector = CONN_SOCKET_7;
- break;
- case 0x580:
- add_to_cpuname("MMX Mobile");
- cpu->connector = CONN_SOCKET_7;
- break;
- case 0x600:
- add_to_cpuname("Pentium Pro A-Step");
- cpu->connector = CONN_SOCKET_8;
- break;
- case 0x610:
- add_to_cpuname("Pentium Pro");
- cpu->connector = CONN_SOCKET_8;
- switch (cpu->stepping) {
- case 1:
- add_to_cpuname(" [B0]");
- switch (cpu->MHz) {
- case 133:
- //sSpec# Q0812, Q0815
- break;
- case 150:
- //sSpec# Q0813, Q0816, SY002, SY011, SY014
- break;
- }
- break;
- case 2:
- add_to_cpuname(" [C0]");
- //sSpec# Q0822, Q0825, Q0826, SY010
- break;
- case 6:
- add_to_cpuname(" [sA0]");
- switch (cpu->MHz) {
- case 166:
- //sSpec# Q0864
- break;
- case 180:
- //sSpec# SY012, Q0858, Q0860, Q0873, Q0910
- break;
- case 200:
- //cache = 256 sSpec# SY013, Q0859, Q0874
- //cache = 512 sSpec# Q0865
- break;
- }
- break;
- case 7:
- add_to_cpuname(" [sA1]");
- switch (cpu->MHz) {
- case 166:
- //sSpec# SY034, SY047, Q0918, Q0929, Q935
- break;
- case 180:
- //sSpec# SY031, SY039, SU103, Q0871, Q0907
- break;
- case 200:
- //cache = 256 sSpec# SY032, SY040, SL245, SL247, SU104, Q076, Q0872, Q0908, Q0909
- //cache = 512 sSpec# SY048, Q0920, Q0924, Q932 , Q936
- break;
- }
- break;
- case 9:
- add_to_cpuname(" [sB1]");
- switch (cpu->MHz) {
- case 166:
- //sSpec# Q008, Q009, SL2FJ, SL22X
- break;
- case 180:
- //sSpec# SL22S, SL22U, SL23L, Q033, Q035
- break;
- case 200:
- //cache = 256 sSpec# L22T, SL22V, SL23M,SL254,SL255,Q034,Q036 ,Q083 ,Q084
- //cache = 512 sSpec# Q010, Q011, SL22Z
- //cache = 1MB sSpec# SL259, SL25A
- break;
- }
- break;
- }
- break;
- case 0x630:
- add_to_cpuname("Pentium II ");
- cpu->connector = CONN_SLOT_1;
- switch (cpu->stepping) {
- case 2:
- add_to_cpuname("Overdrive [tdB0]");
- break;
- case 3:
- add_to_cpuname("(Klamath) [C0]");
- switch (cpu->MHz) {
- case 233:
- //sSpec# SL264, SL268, SL28K
- break;
- case 266:
- //sSpec# SL265, SL269, SL28L
- break;
- case 300:
- //sSpec# SL28R, SL2MZ
- break;
- }
- break;
- case 4:
- add_to_cpuname("(Klamath) [C1]");
- switch (cpu->MHz) {
- case 233:
- //sSpec# SL2HD, SL2HF, SL2QA
- break;
- case 266:
- //sSpec# SL2HC, SL2HE, SL2QB
- break;
- case 300:
- //sSpec# SL2HA, SL2QC
- break;
- }
- break;
- }
- break;
- case 0x640:
- //Does this exist? Its not in Intels spec update.
- cpu->connector = CONN_SLOT_1;
- add_to_cpuname("Pentium II (Deschutes?)");
- break;
- case 0x650:
- cpu->connector = CONN_SLOT_1;
- switch (cpu->cachesize_L2) {
- case 0:
- add_to_cpuname("Celeron (Covington)");
- break;
-
- case 256:
- add_to_cpuname("Mobile Pentium II (Dixon)");
- break;
-
- case 512:
- switch (cpu->stepping) {
- case 0:
- add_to_cpuname("Pentium II [dA0]");
- switch (cpu->MHz) {
- case 266:
- //sSpec# SL2K9
- break;
- case 333:
- //sSpec# SL2KA, SL2QF
- break;
- }
- break;
- case 1:
- add_to_cpuname("Pentium II (Deschutes) [dA1]");
- switch (cpu->MHz) {
- case 300:
- //66 bus sSpec# SL35V, SL2VY
- break;
- case 333:
- //66 bus sSpec# SL2QH, SL2S5, SL2ZP
- break;
- case 350:
- //100Bus - sSpec# SL2ZQ, SL2S6, SL2SF
- break;
- case 400:
- //100Bus - sSpec# Sl2S7, SL2SH
- break;
- }
- break;
- case 2:
- add_to_cpuname("Pentium II (Deschutes) [dB0]");
- switch (cpu->MHz) {
- case 266:
- //66Bus sSpec# SL33D, SL2W7
- break;
- case 300:
- //66Bus - SL2YK, SL2W8
- break;
- case 333:
- //66Bus - SL2KE, SL2TV
- break;
- case 350:
- //100Bus - SL2WZ, SL2U3, SL2U4, SL356, SL37F, SL3FN
- break;
- case 400:
- //100Bus - SL2YM, SL37G, SL2U5, SL2U6, SL357, SL3EE, SL3F9
- break;
- case 450:
- //100Bus - SL2WB, SL37H, SL2U7, SL358
- break;
- }
- break;
- case 3:
- add_to_cpuname("Pentium II (Deschutes) [dB1]");
- switch (cpu->MHz) {
- case 350:
- //100Bus - SL38M, SL36U, SL3J2
- break;
- case 400:
- //100Bus - SL38N, SL38Z, SL3D5
- break;
- }
- break;
- default:
- add_to_cpuname("Pentium II");
- break;
- }
- }
- break;
- case 0x660:
- cpu->connector = CONN_SOCKET_370;
- if (cpu->cachesize_L2 == 128) {
- add_to_cpuname("Celeron (Mendocino)");
- break;
- }
- switch (cpu->stepping) {
+ switch (cpu->model) {
case 0:
- add_to_cpuname("Celeron-A [mA0]");
- break;
- case 5:
- add_to_cpuname("Celeron-A [mB0]");
- break;
- case 0xA:
- add_to_cpuname("Mobile Pentium II [mdA0]");
- break;
- default:
- add_to_cpuname("Celeron / Mobile Pentium II");
- break;
- }
- break;
- case 0x670:
- cpu->connector = CONN_SLOT_1;
- switch (cpu->stepping) {
- case 2:
- // Core=500 FSB=100
- // SL2XU SL3C9 (l2=512)
- // SL2XV SL3CA (l2=1MB)
- // SL2XW SL3CB (l2=2MB)
- add_to_cpuname("Pentium III (Katmai) [kB0]");
- break;
- case 3:
- // Core=550 FSB=100
- // SL3FK SL3D9 SL3AJ SL3Y4 SL3FR SL3LM (l2=512)
- // SL3DA SL3CE SL3TW SL3LN (l2=1mb)
- // SL3DB SL3CF SL3LP (l2=2mb)
- //
- // Core 500 FSB=100
- // SL385 (l2=512)
- // SL386 (l2=1MB)
- // SL387 (l2=2MB)
- add_to_cpuname("Pentium III (Katmai) [kC0]");
- break;
- default:
- add_to_cpuname("Pentium III/Pentium III Xeon");
- break;
- }
- break;
- case 0x680:
- switch (cpu->brand) {
- case 2:
- add_to_cpuname("Pentium III/Pentium III-M (Coppermine)");
- switch (cpu->stepping) {
- case 1:
- add_to_cpuname(" [cA2]");
- break;
- case 3:
- add_to_cpuname(" [cB0]");
- break;
- case 6:
- add_to_cpuname(" [cC0]");
- break;
- case 0xA:
- add_to_cpuname(" [cD0]");
- break;
- }
- break;
- case 3:
- add_to_cpuname("Pentium III Xeon");
- switch (cpu->stepping) {
- case 1:
- // l2=256KB FSB=133
- // Core=600 SL3BJ SL3BK SL3SS
- // Core=667 SL3BL SL3DC SL3ST
- // Core=733 SL3SF SL3SG SL3SU
- // Core=800 SL3V2 SL3V3 SL3VU
- add_to_cpuname(" [A2]");
- break;
- case 3:
- // l2=256 FSB=133
- // Core=600 SL3WM SL3WN
- // Core=667 SL3WP SL3WQ
- // Core=733 SL3WR SL3WS
- // Core=800 SL3WT SL3WU
- // Core=866 SL3WV SL3WW SL4PZ
- // Core=933 SL3WX SL3WY
- add_to_cpuname(" [B0]");
- break;
- case 6:
- // l2=256 FSB=133
- // Core=733 SL4H6 SL4H7
- // Core=800 SL4H8 SL4H9
- // Core=866 SL4HA SL4HB SL4U2
- // Core=933 SL4HC SL4HD SL4R9
- // Core=1000 SL4HE SL4HF
- add_to_cpuname(" [C0]");
- break;
- }
- break;
-
- case 8:
- // cpu->connector = CONN_BGA2; - Could also be Micro-PGA2
- add_to_cpuname("Mobile Pentium III");
- break;
-
- default:
- cpu->connector = CONN_SOCKET_370_FCPGA;
- if (cpu->cachesize_L2 == 128) {
- add_to_cpuname("Celeron");
- } else {
- add_to_cpuname("Pentium III");
- }
-
- add_to_cpuname(" (Coppermine)");
- switch (cpu->stepping) {
- case 1:
- add_to_cpuname(" [cA2]");
- break;
- case 3:
- add_to_cpuname(" [cB0]");
- break;
- case 6:
- add_to_cpuname(" [cC0]");
- break;
- case 0xA:
- add_to_cpuname(" [cD0]");
- break;
- }
- break;
- }
- break;
-
- case 0x690:
-// cpu->connector =
- add_to_cpuname("Pentium M (Banias)");
- break;
-
- case 0x6A0:
- cpu->connector = CONN_SLOT_1;
- switch (cpu->brand) {
- case 0:
- add_to_cpuname("Pentium II (Deschutes)");
+ add_to_cpuname("DX-25/33");
break;
case 1:
- add_to_cpuname("Celeron");
+ add_to_cpuname("DX-50");
break;
case 2:
- add_to_cpuname("Pentium III");
+ add_to_cpuname("SX");
break;
case 3:
- // FSB=100
- add_to_cpuname("Pentium III Xeon");
- switch (cpu->stepping) {
- case 0:
- // Core=700
- // L2=1MB SL3U4 SL3U5 SL4GD SL4GE
- // L2=2MB SL3WZ SL3X2 SL4GF SL4GG
- add_to_cpuname(" [A0]");
- break;
- case 1:
- // Core=700
- // L2=1MB SL49P SL49Q SL4RZ
- // L2=2MB SL49R SL49S SL4R3
- add_to_cpuname(" [A1]");
- break;
- case 4:
- // Core=700
- // L2=1MB SL4XU SL5D4 SL4XV
- // L2=2MB SL4XW SL5D5 SL4XX
- // Core=900
- // L2=2MB SL4XY SL4XZ SL5D3
- add_to_cpuname(" [B0]");
- break;
- }
+ add_to_cpuname("487/DX2");
break;
case 4:
- add_to_cpuname("Pentium III (Cascades)");
- break;
- default:
- add_to_cpuname("Unknown CPU");
+ add_to_cpuname("SL");
break;
- }
- break;
- case 0x6B0:
- switch (cpu->brand) {
- case 1:
- case 3:
- cpu->connector = CONN_SLOT_1;
- add_to_cpuname("Celeron (Tualatin) [tA1/cA2]");
- break;
- case 6:
- cpu->connector = CONN_MICROFCBGA;
- add_to_cpuname("Pentium III-M");
- break;
- default:
- cpu->connector = CONN_SLOT_1;
- switch (cpu->stepping) {
- case 1:
- add_to_cpuname("Pentium III (Tualatin) [tA1/cA2]");
- break;
- case 4:
- add_to_cpuname("Pentium III [B-1]");
- break;
- default:
- add_to_cpuname("Unknown CPU");
- break;
- }
- }
- break;
- case 0x6d0:
- add_to_cpuname("Pentium M ");
- cpu->connector = CONN_MICROFCBGA;
- switch (cpu->stepping) {
- case 1: add_to_cpuname("(Dothan) [A-1]");
- break;
-
- case 2: add_to_cpuname("(Dothan) [A-2]");
- break;
-
- /*
- S-spec Processor Hi-Freq Low-Freq
- Number
- SL7EM 755 2.0GHz 600MHz
- SL7EL 755 2.0GHz 600MHz
- SL7EN 745 1.8GHz 600MHz
- SL7EQ 745 1.8GHz 600MHz
- SL7EP 735 1.7GHz 600MHz
- SL7ER 735 1.7GHz 600MHz
- SL7EG 725 1.6GHz 600MHz
- SL7F2 725 1.6GHz 600MHz
- SL7GL 715 1.5GHz 600MHz
- SL7GK 715 1.5GHz 600MHz
- SL7VC 738 1.4GHz 600MHz
- SL7F4 733 1.1GHz 600MHz
- SL7VD 733 1.1GHz 600MHz
- SL7V2 723 1.0GHz 600MHz
- */
- case 6: add_to_cpuname("(Dothan) [B-1]");
- break;
-
- /*
- FSB=533 2MB L2 90nm
- SL86G 730 1.6GHz 800MHz
- SL7SA 740 1.73GHz 800MHz
- SL7S9 750 1.86GHz 800MHz
- SL7SM 760 2.0GHz 800MHz
- SL7SL 770 2.13GHz 800MHz
- SL7VB 780 2.26GHz 800MHz
- SL86M 730 1.6GHz 800MHz
- SL7S8 740 1.73GHz 800MHz
- SL7SR 750 1.86GHz 800MHz
- Sl7SQ 760 2.0GHz 800MHz
- SL7SP 770 2.13GHz 800MHz
- SL7SN 780 2.26GHz 800MHz
- SL86B 740 1.73GHz 800MHz
- SL86A 750 1.86GHz 800MHz
- SL869 760 2.0GHz 800MHz
- SL868 770 2.13GHz 800MHz
- SL8QK 780 2.26GHz 800MHz
- FSB=400
- SL8QF 778 1.6GHz 600MHz
- SL89X 758 1.5GHz 600MHz
- SL8A3 723 1.0GHz 600MHz
- SL8LM 733J 1.1GHz 600MHz
- SL8A2 733J 1.1GHz 600MHz
- SL89Z 753 1.2GHz 600MHz
- SL8LL 753 1.2GHz 600MHz
- SL8QG 778 1.6GHz 600MHz
- SL89M 758 1.5GHz 600MHz
- SL89R 723 1.0GHz 600MHz
- SL8LT 733J 1.1GHz 600MHz
- SL89Q 733J 1.1GHz 600MHz
- SL89P 753 1.2GHz 600MHz
- SL8LS 753 1.2GHz 600MHz
- SL89N 738 1.4GHz 600MHz
- SL89Y 738 1.4GHz 600MHz
- */
- case 8: add_to_cpuname("(Dothan) [C-0]");
- break;
- }
- break;
-
- case 0x6e0:
- add_to_cpuname("Core ");
- switch (cpu->stepping) {
- case 8:
- switch (cpu->MHz) {
- case 1000:
- // SL99W/SL8W7 533FSB
- add_to_cpuname("Duo U2400/Solo U1300 [C-0]");
- break;
- case 1200:
- // SL8W6 533FSB
- add_to_cpuname("Solo U1400 [C-0]");
- break;
- case 1500:
- // SL8VX 667FSB
- add_to_cpuname("Duo L2300 [C-0]");
- break;
- case 1600:
- // SL9JE/SL9JV/SL8VR/SL8VV/SL8VY/SL8W3/SL8VW 667FSB
- add_to_cpuname("Solo T1300/Duo T2300(E)/Duo L2400");
- break;
- case 1800:
- // SL92X/SL8VQ/SL8VU/SL92V/SL92X 667FSB
- add_to_cpuname("Solo T1400/Duo T2400 [C-0]");
- break;
- case 2000:
- // SL8VP/SL8VT/SL92U/SL92W 667FSB
- add_to_cpuname("Solo T1500/Duo T2500 [C-0]");
- break;
- case 2150:
- // SL8VN/SL8VS 667FSB
- add_to_cpuname("Duo T2600 [C-0]");
- break;
- }
- break;
- case 0xc:
- switch (cpu->MHz) {
- case 1200:
- // SL99V 533FSB
- add_to_cpuname("Duo U2500 [D-0]");
- break;
- case 1800:
- // SL9JU 667FSB
- add_to_cpuname("Duo L2500 [D-0]");
- break;
- case 2300:
- // SL9JP/SL9K4 667FSB
- add_to_cpuname("Duo T2700 [D-0]");
- break;
- }
- }
- break;
-
- case 0x6f0:
- add_to_cpuname("Core 2 ");
- // Do a numerical hack, because they aren't exactly 2100Mhz etc.
- // FIXME: Come up with a better way to do this, easiest if
- // Intel gives us an Extreme chip to compare against others ;-)
- if(cpu->MHz/100 >= 29) {
- add_to_cpuname("Extreme ");
- } else {
- if (cpu->stepping == 7) {
- add_to_cpuname("Quad (Kentsfield)");
- } else {
- add_to_cpuname("Duo ");
- }
- }
- // Check for Thermal Monitor 2 feature bit, because only the
- // non-mobile processors have it
- // TODO: Clean up Feature bit handling
- if(cpu->flags_ecx & (1 << 8)) {
- cpu->connector = CONN_LGA775;
- switch (cpu->MHz) {
- case 1800:
- // SL9SA 1066FSB 2MB L2
- add_to_cpuname("E6300");
- break;
- case 2150:
- // SL9S9 1066FSB 2MB L2
- add_to_cpuname("E6400");
- break;
- case 2400:
- // SL9S8 1066FSB 4MB L2
- add_to_cpuname("E6600");
- break;
- case 2600:
- // SL9S7 1066FSB 4MB L2
- add_to_cpuname("E6700");
- break;
- case 2950:
- // SL9S5 1066FSB 4MB L2
- add_to_cpuname("E6800/X6800");
- break;
- }
- } else {
- cpu->connector = CONN_MICROFCBGA;
- add_to_cpuname("Mobile ");
- switch (cpu->MHz) {
- case 1600:
- // SL9SH/SL9SQ 1.6GHz 667FSB
- add_to_cpuname("T5500");
- break;
- case 1800:
- // SL9SG/SL9SP 1.8GHz 667FSB
- add_to_cpuname("T5600");
- case 2000:
- // SL9SF/SL9SL 667FSB
- add_to_cpuname("T7200");
- break;
- case 2100:
- // SL9SE/SL9SK 667FSB
- add_to_cpuname("T7400");
- break;
- case 2300:
- // SL9SD/SL9SJ 667FSB
- add_to_cpuname("T7600");
- break;
- }
- }
- // TODO: Check that the Mobile chips really are stepping 6 as well.
- // The Sept 06 Core 2 Intel Errata documentation says there are
- // at least B1 and B2 steppings.
- switch(cpu->stepping) {
- case 2:
- // 2M L2
- // SL9TB E4300 1.86GHz
- // SLA3F E4400 2GHz
- // SL9TA E6300 1.86GHz
- // SL9T9 E6400 2.13GHz
- add_to_cpuname(" [L2]");
- break;
- // TODO: B1 as stepping 5 is a 100% guess
case 5:
- add_to_cpuname(" [B1]");
- break;
- case 6:
- // 2M L2
- // SL9SA E6300 1.86GHz
- // SL9S9 E6400 2.13GHz
- //
- // 4M L2
- // SLA4U E6320 1.86GHz
- // SLA4T E6420 2.13GHz
- // SL9S8 E6600 2.4GHz
- // SL9ZL E6700 2.66GHz
- // SL9ZF E6700 2.66GHz
- // SL9S5 X6800 2.93GHz
- add_to_cpuname(" [B2]");
+ add_to_cpuname("SX2");
break;
case 7:
- // SL9UK [B3] 2.93GHz QX6800
- // SL9UL [B3] 2.66GHz QX6700
- // SL9UM [B3] 2.4GHz Q6600
- // SLACP [G0] 2.93GHz QX6800
- break;
- case 0xa:
- // sCode Procname (IDA/HFM)
- // SLA43 T7700 (2.6GHz/2.4GHz)
- // SLA3M T7700 (2.6GHz/2.4GHz)
- // SLA44 T7500 (2.4GHz/2.2GHz)
- // SLA3N T7500 (2.4GHz/2.2GHz)
- // SLA45 T7300 (2.4GHz/2.0GHz)
- // SLA3P T7300 (2.2GHz/2.0GHz)
- // SLA3R L7500 (1.8GHz/1.6GHz)
- // SLA3S L7300 (1.6GHz/1.4GHz)
- // SLA33 X7900 (2.8GHz)
- // SLA6Z X7800 (2.6GHz)
- add_to_cpuname(" [E1]");
+ add_to_cpuname("write-back enhanced DX2");
break;
- case 0xb:
- // SLAA5 2.33GHz E6540
- // SLA9X 2.33GHz E6550
- // SLA9V 2.66GHz E6750
- // SLA9U 3GHz E6850
- // SLAFN 3GHz QX6850
- // SLACQ 2.66GHz Q6700
- // SLACR 2.4GHz Q6600
- //
- // Xeon 7200/7300 series
- // SLA67 2.93GHz X7350 [8M L2]
- // SLA68 2.4GHz E7340 [8M L2]
- // SLA77 2.4GHz E7330 [8M L2]
- // SLA69 2.13GHz E7320 [4M L2]
- // SLA6A 1.6GHz E7310 [4M L2]
- // SLA6B 1.86GHz L7345 [8M L2]
- // SLA6C 2.93GHz E7220 [8M L2]
- // SLA6D 2.4GHz E7210 [8M L2]
- add_to_cpuname(" [G0]");
+ case 8:
+ add_to_cpuname("DX4");
+ cpu->connector = CONN_SOCKET_3;
+ //transistors = 1600000;
+ //fab_process = "0.6 micron CMOS";
+ //die_size = "345 sq. mm";
+ //introduction_date = "March 1994";
break;
- case 0xd:
- // SLA98 E4400 2GHz
- // SLA95 E4500 2GHz
- add_to_cpuname(" [M0]");
+ case 9:
+ add_to_cpuname("write-back enhanced DX4");
+ cpu->connector = CONN_SOCKET_3;
break;
}
break;
- case 0x700: /* Family 7 */
- add_to_cpuname("Itanium");
- break;
-
- case 0xF00: /* Family 15 */
- cpu->connector = CONN_SOCKET_423;
- cpu->datasheet_url = strdup(p4_423_datasheet);
- cpu->errata_url = strdup(p4_errata);
- add_to_cpuname("Pentium 4");
- switch (cpu->stepping) {
- case 7:
- //SL4QD SL4SF = 1.3GHz
- //SL4SG SL4SC = 1.4GHz
- //SL4SH SL4TY = 1.5GHz
- add_to_cpuname(" [B2]");
- break;
- case 0xA:
- //SL5FW SL5GC 1.3GHz
- //SL4WS SL4X2 SL59U SL5N7 1.4GHz
- //SL4WT SL4X3 SL59V SL5NB 1.5GHz
- //SL4WU SL4X4 SL5US SL5UW 1.6GHz
- //SL57W SL57V SL59X SL5N9 1.7GHz
- //SL4WV SL4X5 SL5UT SL5UV 1.8GHz
- add_to_cpuname(" [C1]");
+ case 5: add_to_cpuname("Pentium ");
+ switch (cpu->model) {
+ case 0:
+ add_to_cpuname("A-step");
+ cpu->connector = CONN_SOCKET_4;
break;
- }
- break;
-
- case 0xF10:
- cpu->connector = CONN_SOCKET_423;
- add_to_cpuname("Pentium 4 (Willamette)");
- cpu->datasheet_url = strdup(p4_423_datasheet);
- cpu->errata_url = strdup(p4_errata);
- switch (cpu->stepping) {
case 1:
- //400FSB 256K L2
- //SSpec MHz L3
- //SL5G8 1.6 1M
- //SL5S4 1.6 1M
- //SL5FZ 1.4 512K
- //SL5RZ 1.4 512K
- //SL5G2 1.5 512K
- //SL5RW 1.5 512K
- add_to_cpuname(" [C0]");
+ add_to_cpuname("60/66");
+ cpu->connector = CONN_SOCKET_4;
break;
case 2:
- //SL5TG SL5UE 1.4GHz
- //SL5SX SL5TJ SL5UF SL62Y SL5TN 1.5GHz
- //SL5VL SL5UL SL5VH SL5UJ 1.6GHz
- //SL5SY SL5TK SL5UG SL62Z 1.7GHz
- //SL5VM SL5VM SL5VJ SL5UK 1.8GHz
- //SL5VN SL5WH SL5VK SL5WG 1.9GHz
- //SL5SZ SL5TQ SL5TL 2GHz
- add_to_cpuname(" [D0]");
+ add_to_cpuname("75-200");
+ cpu->connector = CONN_SOCKET_5_7;
break;
case 3:
- //SL6BC SL679 1.6GHz
- //SL6BD SL67A 1.7GHz
- //SL6BE SL78B 1.8GHz
- //SL6BF SL67C 1.9GHz
- add_to_cpuname(" [E0]");
- break;
- }
- break;
- case 0xF20:
- cpu->connector = CONN_SOCKET_478;
- cpu->datasheet_url = strdup(p4_478_datasheet);
- cpu->errata_url = strdup(p4_errata);
- switch (cpu->brand) {
- case 15:
- add_to_cpuname("Celeron (P4 core)");
- break;
- case 7:
- default:
- add_to_cpuname("Pentium 4 (Northwood)");
- break;
- }
- switch (cpu->stepping) {
- case 2:
- //512K L2
- // L3
- //SL6GZ 1.5 1M
- //SL6KB 1.5 1M
- //SL6H2 1.9 2M
- //SL6KC 1.9 2M
- //SL66Z 2.0 1M
- //SL6KD 2.0 1M
- add_to_cpuname(" [A0]");
+ add_to_cpuname("Overdrive");
+ cpu->connector = CONN_SOCKET_4;
break;
case 4:
- //SL66B 1.6GHz
- //SL63X SL62P SL6BQ 1.8GHz
- //SL6BR SL5YR 2GHz
- //SL5YS SL6BS SL5ZU 2.2GHz
- //SL6B3 SL67Y 2.26GHz (533MHz FSB)
- //SL6BT SL65R SL67R 2.4GHz (400MHz FSB)
- //SL6B4 SL67Z 2.4GHz (533MHz FSB)
- //SL6B5 SL6B2 2.53GHz (533MHz FSB)
- add_to_cpuname(" [B0]");
- break;
- case 5:
- /*[M0] */
- //SL6Z3 2.4GHz (800FSB)
- //SL6Z5 2.8GHz (800FSB)
- /* P4 Extreme edition.*/
- //SL7AA 3.2GHz (800FSB) 2MB L3 cache
- //SL7CH 3.4GHz (800FSB) 2MB L3 cache
-
- /* 400FSB B1 512K L2 */
- //SL6YJ 2.0 1M L3
- //SL6Z6 2.0 1M L3
- //SL6Z2 2.5 1M L3
- //SL6Z7 2.5 1M L3
- //SL6YL 2.8 2M L3
- //SL6Z8 2.8 2M L3
- add_to_cpuname(" [M0]");
- break;
- case 6:
- //400FSB 512K L2
- //SL79V 3.0 4M L3
- //SL79Z 2.7 2M L3
- //SL7A5 2.2 2M L3
- add_to_cpuname(" [C0]");
+ add_to_cpuname("MMX");
+ cpu->connector = CONN_SOCKET_7;
+ //transistors = 4500000;
+ //fab_process = "0.35 micron CMOS";
+ //die_size = "140 sq.mm";
+ //introduction_date = "June 1997";
break;
case 7:
- //SL6HL SL6K6 2.8GHz (533MHz FSB)
- //SL6LA SL6S6 1.8GHz
- //SL6GQ SL6S7 SL6E7 2GHz
- //SL6GR SL6SB SL6EB 2.2GHz
- //SL6DU SL6RY SL6EE 2.26GHz (533FSB)
- //SL6EF SL6DV SL6S9 SL6RZ SL6E9 2.4GHz (533FSB)
- //SL6SA 2.5GHz (400FSB)
- //SL6EG SL6S2 SL6DW 2.53GHz (533FSB)
- //SL6SB 2.6GHz (400FSB)
- //SL6S3 SL6SK 2.66GHz (533FSB)
- //SL6S4 SL6SL 2.8GHz (533FSB)
- //SL6S5 SL6K7 SL6SM SL6JJ 3.06GHz (533FSB)
- add_to_cpuname(" [C1]");
+ add_to_cpuname("Mobile");
+ cpu->connector = CONN_SOCKET_7;
break;
- case 9:
- //SL6QL 1.8GHz
- //SL6QM SL6PK 2.0GHz
- //SL6QN SL6PL 2.2GHz
- //SL6QR SL6PB 2.26GHz (533FSB)
- //SL6QP SL6PM 2.4GHz
- //SL6QB SL6PC 2.4GHz (533FSB)
- //SL6WF SL6WR 2.4GHz (800FSB)
- //SL6QQ 2.5GHz
- //SL6Q9 SL6PD 2.53GHz (533FSB)
- //SL6QR 2.6GHz
- //SL6WH SL6WS 2.6GHz (800FSB)
- //SL6QA SL6PE 2.66GHz (533FSB)
- //SL6QB SL6PF 2.8GHz (533FSB)
- //SL6WJ SL6WT 2.8GHz (800FSB)
- //SL6WU SL6WK 3GHz (800FSB)
- //SL6QC SL6PG 3.06GHz (533FSB)
- //SL6WG SL6WE 3.2GHz (800FSB)
- //SL793 3.4GHz (800FSB)
- add_to_cpuname(" [D1]");
+ case 8:
+ add_to_cpuname("MMX Mobile");
+ cpu->connector = CONN_SOCKET_7;
break;
}
break;
- case 0xF30:
- switch (cpu->stepping) {
- case 3:
- /*
- sspec speed fsb l2 90nm
- SL7D7 2.26GHz 533 512K
- SL7FY 2.4GHz 800 1M
- SL7E8 2.4GHz 533 1M
- SL7E9 2.66GHz 533 1M
- SL7D8 2.8GHz 533 1M
- SL79K 2.8GHz 800 1M
- SL79L 3.0GHz 800 1M
- SL79M 3.2GHz 800 1M
- SL7B8 3.2GHz 800 1M
- SL7B9 3.4GHz 800 1M
- SL7AJ 3.4GHz 800 1M
- process = "0.09u";
- 125 million transistors
- 112mm2 die size
- pipeline_stages=31
- */
- add_to_cpuname("Pentium 4 (Prescott) [C0]");
- break;
- case 4:
- /*
- 1M L2 90nm
- sspec speed fsb
- SL7E2 2.8GHz 533
- SL7E3 2.8GHz 800
- SL7KA 2.8GHz 800
- SL7K9 2.8GHz 533
- SL7E4 3.0GHz 800
- SL7KB 3.0GHz 800
- SL7L4 3.0GHz 800
- SL7L5 3.2GHz 800
- SL7E5 3.2GHz 800
- SL7KC 3.2GHz 800
- SL7E6 3.4GHz 800
- SL7KD 3.4GHz 800
- SL7YP 2.4GHz 533
- SL7YU 2.66GHz 533
- SL7J4 2.8GHz 533
- SL7J5 2.8GHz 800
- SL7KH 2.8GHz 533
- SL7KJ 2.8GHz 800
- SL7YV 2.93GHz 533
- SL7J6 3.0GHz 800
- SL7KK 3.0GHz 800
- SL7J7 3.2GHz 800
- SL7KL 3.2GHz 800
- SL7LA 3.2GHz 800
- SL7J8 3.4GHz 800
- SL7KM 3.4GHz 800
- SL7L8 3.4GHz 800
- SL7J9 3.6GHz 800
- SL7KN 3.6GHz 800
- SL7L9 3.6GHz 800
- */
- add_to_cpuname("Pentium 4 (Prescott) [D0]");
- break;
- }
- break;
+ case 0x6:
+ if (cpu->emodel == 0)
+ Identify_Intel_family6pentium(cpu);
+ else
+ Identify_Intel_family6core(cpu);
- case 0xF40:
- add_to_cpuname("Pentium 4 ");
- switch (cpu->stepping) {
- case 1:
- /*
- 1M L2 90nm
- SL88F 2.4GHz 533
- SL8B3 2.66GHz 533
- SL88G 2.8GHz 533
- SL88H 2.8GHz 800
- SL7PL 2.8GHz 800
- SL7PK 2.8GHz 533
- SL7PM 3GHz 800
- SL88J 3GHz 800
- SL7PN 3.2GHz 800
- SL88K 3.2GHz 800
- SL88L 3.4GHz 800
- SL7PP 3.4GHz 800
- SL7PT 2.66GHz 533
- SL82P 2.8GHz 800
- SL7PR 2.8GHz 800
- SL8HX 2.8GHz 800
- SL85U 2.66GHz 533
- SL8J8 2.66GHz 533
- SL85V 2.93GHz 533
- SL8J9 2.93GHz 533
- SL87L 3.06GHz 533
- SL8JA 3.06GHz 533
- SL82X 3.0GHz 800
- SL7PU 3.0GHz 800
- SL8HZ 3.0GHz 800
- SL7PW 3.2GHz 800
- SL7PX 3.2GHz 800
- SL82Z 3.2GHz 800
- SL8J2 3.2GHz 800
- SL7PY 3.4GHz 800
- SL7PZ 3.4GHz 800
- SL833 3.4GHz 800
- SL7ZW 3.4GHz 800
- SL8J5 3.4GHz 800
- SL84X 3.6GHz 800
- SL7Q2 3.6GHz 800
- SL7NZ 3.6GHz 800
- SL8J6 3.6GHz 800
- SL82U 3.8GHz 800
- SL84Y 3.8GHz 800
- SL7P2 3.8GHz 800
- SL8J7 3.8GHz 800
- */
- /*
- 8MB L3 [C-0]
- SL8EY 3.3GHz 667
- SL8EW 3GHz 667
- 4MB L3
- SL8ED 2.8GHz 667
- */
- add_to_cpuname("(Prescott) [E0]");
- break;
- case 3:
- /*
- 2M L2 90nm
- SL7Z9 3.0GHz 800
- SL7Z8 3.2GHz 800
- SL8Z7 3.4GHz 800
- SL7Z5 3.6GHz 800
- SL7Z4 3.73GHz 800
- SL7Z3 3.8GHz 800
- */
- add_to_cpuname("(Prescott) [N0]");
- break;
- case 4:
- /*
- 1Mx2 L2 800MHz FSB
- SL88T 2.8GHz
- SL88S 3GHz
- SL88R 3.2GHz
- SL8FK 3.2GHz
- */
- add_to_cpuname("Extreme Edition [A0]");
- break;
- default:
- add_to_cpuname("D (Foster)");
- break;
- }
+ intel_nameptr += strlen(cpu->name); // EWW
break;
- case 0xF50:
- cpu->connector = CONN_SOCKET_603;
-// cpu->datasheet_url = strdup(p4_478_datasheet);
-// cpu->errata_url = strdup(p4_errata);
- add_to_cpuname("Pentium 4 Xeon (Foster)");
- break;
- default:
- add_to_cpuname("Unknown CPU");
+ case 0x7:
+ add_to_cpuname("Itanium");
break;
- }
- switch (cpu->type) {
- case 0:
- add_to_cpuname(" Original OEM");
- break;
- case 1:
- add_to_cpuname(" Overdrive");
- break;
- case 2:
- add_to_cpuname(" Dual-capable");
- break;
- case 3:
- add_to_cpuname(" Reserved");
+ case 0xF:
+ Identify_Intel_family15(cpu);
+ intel_nameptr += strlen(cpu->name); // EWW
break;
}
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/info.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: info.c,v 1.10 2004/10/06 21:19:05 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -10,7 +8,6 @@
* References:
* http://developer.intel.com/
* http://microcodes.sourceforge.net/CPUID.htm
- *
*/
#include <stdio.h>
@@ -21,62 +18,103 @@
/* Decode Pentium III CPU serial number */
void decode_serial_number(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
- unsigned long signature;
+ char *p = cpu->serialno;
+ unsigned int eax, ebx, ecx, edx;
+ unsigned int signature;
- if (cpu->family!=6)
+ if (cpu->maxi < 3)
return;
- switch (cpu->model) {
- case 7:
- case 8:
- case 10:
- case 11:
- if (cpu->maxi < 3)
- return;
-
- cpuid (cpu->number, 1, &eax, NULL, NULL, NULL);
- signature = eax;
-
- cpuid (cpu->number, 3, &eax, &ebx, &ecx, &edx);
- printf ("Processor serial: ");
- printf ("%04lX", signature >> 16);
- printf ("-%04lX", signature & 0xffff);
- printf ("-%04lX", edx >> 16);
- printf ("-%04lX", edx & 0xffff);
- printf ("-%04lX", ecx >> 16);
- printf ("-%04lX\n", ecx & 0xffff);
- return;
- default:
- return;
- }
-}
-
-void display_Intel_info (struct cpudata *cpu)
-{
- unsigned long ebx;
+ cpuid(cpu->number, 1, &eax, NULL, NULL, NULL);
+ signature = eax;
- printf ("Family: %u Model: %u Stepping: %u Type: %u Brand: %u\n",
- cpu->family, cpu->model, cpu->stepping, cpu->type, cpu->brand);
- printf ("CPU Model: %s\n", cpu->name);
+ cpuid(cpu->number, 3, &eax, &ebx, &ecx, &edx);
+ p += sprintf(p, "%04X", signature >> 16);
+ p += sprintf(p, "-%04X", signature & 0xffff);
+ p += sprintf(p, "-%04X", edx >> 16);
+ p += sprintf(p, "-%04X", edx & 0xffff);
+ p += sprintf(p, "-%04X", ecx >> 16);
+ p += sprintf(p, "-%04X\n", ecx & 0xffff);
- /* Pentium4 and Banias have cpu name. */
- if (cpu->family == 0xF || (cpu->family == 6 && cpu->model == 9))
- get_model_name (cpu);
+ printf("Processor serial: %s\n", cpu->serialno);
+}
- decode_feature_flags (cpu);
+void display_Intel_info(struct cpudata *cpu)
+{
+ printf("Type: %u (", cpu->type);
+ switch (cpu->type) {
+ case 0: printf("Original OEM");
+ break;
+ case 1: printf("Overdrive");
+ break;
+ case 2: printf("Dual-capable");
+ break;
+ case 3: printf("Reserved");
+ break;
+ }
+ printf(")\tBrand: %u (", cpu->brand);
+ switch (cpu->brand) {
+ case 0: printf("Unsupported");
+ break;
+ case 1:
+ case 0xA:
+ case 0x14: printf("Intel® Celeron® processor");
+ break;
+ case 2:
+ case 4: printf("Intel® Pentium® III processor");
+ break;
+ case 3: if (tuple(cpu) == 0x6b1)
+ printf("Intel® Celeron® processor");
+ else
+ printf("Intel® Pentium® III Xeon processor");
+ break;
+ case 6: printf("Mobile Intel® Pentium® III processor");
+ break;
+ case 7:
+ case 0xF:
+ case 0x17: printf("Mobile Intel® Celeron® processor");
+ break;
+ case 8: if (tuple(cpu) >= 0xf13)
+ printf("Intel® genuine processor");
+ else
+ printf("Intel® Pentium® 4 processor");
+ break;
+ case 9: printf("Intel® Pentium® 4 processor");
+ break;
+
+ case 0xb: if (tuple(cpu) <0xf13)
+ printf("Intel® Xeon processor MP");
+ else
+ printf("Intel® Xeon processor");
+ break;
+ case 0xc: printf("Intel® Xeon processor");
+ break;
+ case 0xe: if (tuple(cpu) <0xf13)
+ printf("Intel® Xeon processor");
+ else
+ printf("Mobile Intel® Pentium® 4 processor-M");
+ break;
+ case 0x11:
+ case 0x15: printf("Mobile Genuine Intel® processor");
+ break;
+ case 0x12: printf("Intel® Celeron® M processor");
+ break;
+ case 0x13: printf("Mobile Intel® Celeron® processor");
+ break;
+ case 0x16: printf("Intel® Pentium® M processor");
+ break;
+ default: printf("unknown");
+ break;
+ }
+ printf(")\n");
if (show_msr) {
- if (cpu->family==0xf)
+ if (cpu->family == 0xf)
dump_p4_MSRs(cpu);
- if (cpu->family==0x6 && (cpu->model == 9 || cpu->model == 13))
+ if (cpu->family == 0x6 && (cpu->model == 9 || cpu->model == 13))
dump_centrino_MSRs(cpu);
}
- decode_Intel_caches(cpu, 1);
-
- decode_serial_number(cpu);
-
if (show_eblcr) {
if (cpu->family == 6 && cpu->model >= 3) {
unsigned long long eblcr;
@@ -89,21 +127,8 @@
if (show_bluesmoke)
decode_Intel_bluesmoke(cpu->number, cpu->family);
- /* Hyper-Threading Technology */
- if (cpu->flags_edx & (1 << 28)) {
- int nr_ht;
- int phys_id;
- cpuid(cpu->number, 1, NULL, &ebx, NULL, NULL);
-
- nr_ht = (ebx >> 16) & 0xFF;
- phys_id = (ebx >> 24) & 0xFF;
-
- if (!nr_ht)
- nr_ht = 1;
- printf ("The physical package supports "
- "%d logical processors \n\n", nr_ht);
- }
-
if (show_microcode)
decode_microcode(cpu);
+
+ show_intel_topology(cpu);
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Intel/microcode.c
^
|
| @@ -1,12 +1,9 @@
/*
- * $Id: microcode.c,v 1.3 2003/04/11 00:17:20 davej Exp $
- * This file is part of x86info.
* (C) 2002 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Intel P6 microcode information.
- *
*/
#include <stdio.h>
@@ -17,7 +14,7 @@
void decode_microcode(struct cpudata *cpu)
{
- unsigned long long val=0;
+ unsigned long long val = 0;
int ver;
if (!user_is_root)
@@ -26,10 +23,10 @@
if (cpu->family < 6)
return;
- if (read_msr (cpu->number, MSR_IA32_UCODE_REV, &val)==1) {
+ if (read_msr (cpu->number, MSR_IA32_UCODE_REV, &val) == 1) {
ver = val >>32;
if (ver>0)
- printf ("Microcode version: 0x%016llx\n", val >>32);
- printf ("\n");
+ printf("Microcode version: 0x%016llx\n", val >>32);
+ printf("\n");
}
}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/Intel/topology.c
^
|
| @@ -0,0 +1,118 @@
+/*
+ * (C) 2008 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Intel multicore/multithread determination.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <strings.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+
+static int fls(int x)
+{
+ int r = 32;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff0000u)) {
+ x <<= 16;
+ r -= 16;
+ }
+ if (!(x & 0xff000000u)) {
+ x <<= 8;
+ r -= 8;
+ }
+ if (!(x & 0xf0000000u)) {
+ x <<= 4;
+ r -= 4;
+ }
+ if (!(x & 0xc0000000u)) {
+ x <<= 2;
+ r -= 2;
+ }
+ if (!(x & 0x80000000u)) {
+ x <<= 1;
+ r -= 1;
+ }
+ return r;
+}
+
+
+/* Determine the width of the bit field that can represent the value item. */
+static unsigned int find_maskwidth(unsigned int item)
+{
+ unsigned int MaskWidth = 0;
+
+ MaskWidth = fls(item)-1;
+ return MaskWidth;
+}
+
+/* Extract the subset of bit field from the 8-bit value FullID. It returns the 8-bit sub ID value */
+static unsigned char GetSubID(unsigned char FullID, unsigned char MaxSubIDvalue, unsigned char ShiftCount)
+{
+ unsigned int MaskWidth, MaskBits, SubID;
+
+ MaskWidth = find_maskwidth(MaxSubIDvalue);
+ MaskBits = ((unsigned char) (0xff << ShiftCount)) ^ ((unsigned char) (0xff << (ShiftCount + MaskWidth))) ;
+ SubID = (FullID & MaskBits) >> ShiftCount;
+ return SubID;
+}
+
+
+void show_intel_topology(struct cpudata *cpu)
+{
+ unsigned int eax, ebx, ecx, edx;
+ unsigned int MaxLPPerCore;
+ unsigned int smt_id, core_id, package_id;
+ unsigned int shift;
+
+ cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
+
+ /* Find the max number of logical processors per physical package. */
+ if (cpu->flags_edx & (1 << 28))
+ cpu->nr_logical = (ebx >> 16) & 0xff;
+ else
+ cpu->nr_logical = 1;
+
+ /* Find the max number of processor cores per physical processor package. */
+ if (cpu->maxi >= 4) {
+ cpuid4(cpu->number, 0, &eax, &ebx, &ecx, &edx);
+ if (eax & 0x1f)
+ cpu->nr_cores = ((eax >> 26) + 1);
+ } else {
+ cpu->nr_cores = 1;
+ }
+
+ //MaxLPPerCore = MaxLogicalProcPerPhysicalProc() / MaxCorePerPhysicalProc();
+ MaxLPPerCore = cpu->nr_logical / cpu->nr_cores;
+ printf("Number of cores per physical package=%d\n", cpu->nr_cores); // 8
+ printf("Number of logical processors per socket=%d\n", cpu->nr_logical); // 16
+ printf("Number of logical processors per core=%d\n", MaxLPPerCore); // 2
+
+ /* test for hyperthreading. */
+ if (cpu->flags_edx & (1 << 28)) {
+ // test that there's more logical processor IDs with the same physical ID
+ // than the number of cores per physical processors.
+ }
+
+ smt_id = GetSubID(cpu->apicid, cpu->nr_logical, 0);
+ shift = find_maskwidth(cpu->nr_logical);
+ core_id = GetSubID(cpu->apicid, cpu->nr_cores, shift);
+ shift += find_maskwidth(cpu->nr_cores);
+ package_id = GetSubID(cpu->apicid, MaxLPPerCore, shift);
+
+ printf("APIC ID: 0x%x\t", cpu->apicid);
+ printf("Package: %u Core: %u SMT ID %u\n", package_id, core_id, smt_id);
+}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/Makefile
^
|
| @@ -1,89 +1,122 @@
-CFLAGS = -Wall -W -Wshadow -g -O2
+CFLAGS = -g -O2 -Werror -Wall -Wshadow -Wextra -Wmissing-declarations -Wdeclaration-after-statement -Wredundant-decls
CC = gcc
SHELL = /bin/sh
-all: x86info test
-
-OBJS =\
- AMD/identify.o\
- AMD/bluesmoke.o\
- AMD/MSR-Athlon.o\
- AMD/MSR-K6.o\
- AMD/powernow.o\
- AMD/dumppsb.o\
- AMD/bugs.o\
-\
- Cyrix/identify.o\
-\
- Intel/identify.o\
- Intel/info.o\
- Intel/bluesmoke.o\
- Intel/cachesize.o\
- Intel/eblcr.o\
- Intel/MSR-P4.o\
- Intel/MSR-P6.o\
- Intel/MSR-PM.o\
- Intel/microcode.o\
-\
- IDT/identify.o\
- IDT/MSR-C3.o\
- IDT/longhaul.o\
- IDT/powersaver.o\
-\
- NatSemi/identify.o\
-\
- RiSE/identify.o\
-\
- SiS/identify.o\
-\
- x86info.o\
- havecpuid.o\
- cpuid.o\
- cpuid_UP.o\
- features.o\
- identify.o\
- rdmsr.o\
- binary.o\
- mptable.o\
- get_model_name.o\
- mtrr.o \
- connector.o\
-\
- bench/benchmarks.o\
- bench/MHz.o
-
-x86info: $(OBJS)
- $(CC) $(CFLAGS) -o x86info $(OBJS)
.c.o:
- $(CC) $(CFLAGS) -o $@ -c $<
+ $(CC) $(CFLAGS) -MMD -o $@ -c $<
+ @cp $*.d $*.P; \
+ sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
+ -e '/^$$/ d' -e 's/$$/ :/' < $*.d >> $*.P; \
+ rm -f $*.d
.S.o:
$(CC) $(CFLAGS) -o $@ -c $<
+
+all: x86info test lsmsr
+
+
+LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h generic_msr.h
+
+%.h: %.regs scripts/createheader.py
+ python scripts/createheader.py $< `basename $< .regs` >$@
+
+LSMSR_SRC =\
+ lsmsr.c\
+ cpuid.c\
+ havecpuid.c
+
+LSMSR_OBJS = $(LSMSR_SRC:%.c=%.o)
+
+lsmsr: $(LSMSR_TMP_HEADERS) $(LSMSR_OBJS)
+ $(CC) $(CFLAGS) -o lsmsr $(LSMSR_OBJS)
+
+-include $(LSMSR_SRC:%.c=%.P)
+
+X86INFO_SRC =\
+ AMD/identify.c\
+ AMD/bluesmoke.c\
+ AMD/MSR-Athlon.c\
+ AMD/MSR-K6.c\
+ AMD/powernow.c\
+ AMD/dumppsb.c\
+ AMD/bugs.c\
+\
+ Cyrix/identify.c\
+\
+ Intel/identify.c\
+ Intel/identify-family6.c\
+ Intel/identify-family6-extended.c\
+ Intel/identify-family15.c\
+ Intel/info.c\
+ Intel/bluesmoke.c\
+ Intel/cachesize.c\
+ Intel/eblcr.c\
+ Intel/MSR-P4.c\
+ Intel/MSR-P6.c\
+ Intel/MSR-PM.c\
+ Intel/microcode.c\
+ Intel/topology.c\
+\
+ Centaur/identify.c\
+ Centaur/MSR-C3.c\
+ Centaur/longhaul.c\
+ Centaur/powersaver.c\
+\
+ NatSemi/identify.c\
+\
+ RiSE/identify.c\
+\
+ SiS/identify.c\
+\
+ x86info.c\
+ havecpuid.c\
+ cpuid.c\
+ dumpregs.c\
+ features.c\
+ identify.c\
+ rdmsr.c\
+ binary.c\
+ mptable.c\
+ get_model_name.c\
+ mtrr.c \
+ connector.c\
+\
+ bench/benchmarks.c\
+ bench/MHz.c
+
+X86INFO_OBJS = $(X86INFO_SRC:%.c=%.o)
+
+x86info: $(X86INFO_OBJS)
+ $(CC) $(CFLAGS) -o x86info $(X86INFO_OBJS)
+
+-include $(X86INFO_SRC:%.c=%.P)
+
+
nodes:
scripts/makenodes
test:
scripts/testnodes
-VERSION=1.21
+VERSION=1.24
release:
git repack -a -d
git-prune-packed
- git-tar-tree HEAD x86info-$(VERSION) | gzip -9 > x86info-$(VERSION).tgz
+ git-archive --format=tar --prefix=x86info-$(VERSION)/ HEAD | gzip -9 > x86info-$(VERSION).tgz
clean:
@find . -name "*.o" -exec rm {} \;
@find . -name "*~" -exec rm {} \;
+ @find . -name "*.P" -exec rm {} \;
@rm -f x86info x86info.exe
-
-C_SRC = *.c AMD/*.c Cyrix/*.c Intel/*.c NatSemi/*.c RiSE/*.c SiS/*.c IDT/*.c
+ @rm -f lsmsr $(LSMSR_TMP_HEADERS)
splint:
- splint +posixlib -badflag -fileextensions -type -nullassign -boolops -showcolumn -sysunrecog -fullinitblock -onlytrans -unrecog -usedef -statictrans -compdestroy -predboolint -predboolothers -D__`uname -m`__ $(C_SRC)
+ splint +posixlib -badflag -fileextensions -type -nullassign -boolops -showcolumn -sysunrecog -fullinitblock -onlytrans -unrecog -usedef -statictrans -compdestroy -predboolint -predboolothers -D__`uname -m`__ $(X86INFO_SRC)
sparse:
- sparse $(C_SRC)
+ sparse $(X86INFO_SRC)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/NatSemi/identify.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: identify.c,v 1.6 2002/11/11 20:02:55 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -13,21 +11,9 @@
static char *NatSemi_nameptr;
#define add_to_cpuname(x) NatSemi_nameptr += snprintf(NatSemi_nameptr, sizeof(x), "%s", x);
-void Identify_NatSemi (struct cpudata *cpu)
+void identify_natsemi(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
-
NatSemi_nameptr = cpu->name;
- cpu->vendor = VENDOR_NATSEMI;
-
- /* Do standard stuff */
- if (cpu->maxi < 1)
- return;
-
- cpuid (cpu->number, 1, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
switch (tuple(cpu) & 0xff0) {
case 0x540: add_to_cpuname("Geode GX1");
@@ -36,14 +22,3 @@
break;
}
}
-
-
-void display_NatSemi_info(struct cpudata *cpu)
-{
- printf ("Family: %u Model: %u Stepping: %u\n",
- cpu->family, cpu->model, cpu->stepping);
- printf ("CPU Model : %s\n", cpu->name);
- get_model_name (cpu);
-
- decode_feature_flags (cpu);
-}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/README
^
|
| @@ -1,4 +1,4 @@
-x86info v1.21 http://www.codemonkey.org.uk/projects/x86info
+x86info v1.24 http://www.codemonkey.org.uk/projects/x86info
Dave Jones <davej@redhat.com>
Somewhere in the mists of time, there was a program by Phil Karn (KA9Q)
@@ -14,12 +14,13 @@
Features:
- SMP support.
- - Recognition of all Intel/AMD/IDT/Cyrix/VIA CPUs.
+ - Recognition of all Intel/AMD/Centaur/Cyrix/VIA CPUs.
- Parsing of model specific registers.
- Approximation of current CPU MHz.
+Requirements:
+* On Linux, at least version 2.4 of glibc is required.
-Caveats:
* For usage of the MSR / SMP functions, x86info needs the
x86 cpuid driver provided with the Linux kernel since 2.2.18 / 2.4.0,
and the appropriate nodes in /dev
@@ -36,10 +37,9 @@
* If you are using the cpuid / msr drivers built as modules
as opposed to built into the kernel, then you should ensure
- the following is in your /etc/modules.conf
+ the following is in your /etc/modprobe.conf:
alias char-major-202 msr
alias char-major-203 cpuid
Info on the command line switches can be found in the man page.
-
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/RiSE/identify.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: identify.c,v 1.11 2002/11/11 20:02:56 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -13,43 +11,20 @@
static char *rise_nameptr;
#define add_to_cpuname(x) rise_nameptr += snprintf(rise_nameptr, sizeof(x), "%s", x);
-void Identify_RiSE (struct cpudata *cpu)
+void identify_RiSE(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
-
rise_nameptr = cpu->name;
- cpu->vendor = VENDOR_RISE;
-
- /* Do standard stuff */
- if (cpu->maxi < 1)
- return;
-
- cpuid (cpu->number, 1, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
switch (tuple(cpu) & 0xff0) {
- case 0x500: add_to_cpuname("iDragon (0.25um)");
- break;
- case 0x520: add_to_cpuname("iDragon (0.18um)");
- break;
- case 0x580: add_to_cpuname("iDragon II (0.25um)");
- break;
- case 0x590: add_to_cpuname("iDragon II (0.18um)");
- break;
- default: add_to_cpuname("Unknown CPU");
- break;
+ case 0x500: add_to_cpuname("iDragon (0.25um)");
+ break;
+ case 0x520: add_to_cpuname("iDragon (0.18um)");
+ break;
+ case 0x580: add_to_cpuname("iDragon II (0.25um)");
+ break;
+ case 0x590: add_to_cpuname("iDragon II (0.18um)");
+ break;
+ default: add_to_cpuname("Unknown CPU");
+ break;
}
}
-
-
-void display_RiSE_info(struct cpudata *cpu)
-{
- printf ("Family: %u Model: %u Stepping: %u\n",
- cpu->family, cpu->model, cpu->stepping);
- printf ("CPU Model : %s\n", cpu->name);
- get_model_name (cpu);
-
- decode_feature_flags (cpu);
-}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/SiS/identify.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: identify.c,v 1.1 2003/04/11 00:10:42 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -13,21 +11,9 @@
static char *sis_nameptr;
#define add_to_cpuname(x) sis_nameptr += snprintf(sis_nameptr, sizeof(x), "%s", x);
-void Identify_SiS (struct cpudata *cpu)
+void identify_sis(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
-
sis_nameptr = cpu->name;
- cpu->vendor = VENDOR_SIS;
-
- /* Do standard stuff */
- if (cpu->maxi < 1)
- return;
-
- cpuid (cpu->number, 1, &eax, &ebx, &ecx, &edx);
- cpu->stepping = eax & 0xf;
- cpu->model = (eax >> 4) & 0xf;
- cpu->family = (eax >> 8) & 0xf;
switch (tuple(cpu)) {
case 0x505: add_to_cpuname("SiS55x");
@@ -36,14 +22,3 @@
break;
}
}
-
-
-void display_SiS_info(struct cpudata *cpu)
-{
- printf ("Family: %u Model: %u Stepping: %u\n",
- cpu->family, cpu->model, cpu->stepping);
- printf ("CPU Model : %s\n", cpu->name);
- get_model_name (cpu);
-
- decode_feature_flags (cpu);
-}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/bench/MHz.c
^
|
| @@ -1,68 +1,60 @@
/*
- * $Id: MHz.c,v 1.3 2003/06/09 22:02:36 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
- *
- * Estimate CPU MHz routine by Andrea Arcangeli <andrea@suse.de>
- * Small changes by David Sterba <sterd9am@ss1000.ms.mff.cuni.cz>
- *
*/
#include <stdio.h>
#include <sys/time.h>
-#include <string.h>
#include <unistd.h>
+#include <stdlib.h>
+
+#include <string.h>
+#include <signal.h>
#include "../x86info.h"
+#include "bench.h"
+
+static volatile int nosignal = 0;
-unsigned long long int rdtsc(void)
+static void sighandler(int sig __attribute__((unused)))
{
- unsigned long long int x;
- __asm__ volatile (".byte 0x0f, 0x31" : "=A" (x));
- return x;
+ nosignal = 1;
}
void estimate_MHz(struct cpudata *cpu)
{
- struct timezone tz;
- struct timeval tvstart, tvstop;
unsigned long long int cycles[2]; /* gotta be 64 bit */
- unsigned long microseconds; /* total time taken */
- unsigned long eax, ebx, ecx, edx;
- unsigned long freq = 1;
+ unsigned int eax, ebx, ecx, edx;
+ unsigned long r;
/* Make sure we have a TSC (and hence RDTSC) */
- cpuid (cpu->number, 1, &eax, &ebx, &ecx, &edx);
- if ((edx & (1<<4))==0) {
- printf ("No TSC, MHz calculation cannot be performed.\n");
+ cpuid(cpu->number, 1, &eax, &ebx, &ecx, &edx);
+ if ((edx & (1<<4)) == 0) {
+ printf("No TSC, MHz calculation cannot be performed.\n");
cpu->MHz = 0;
return;
}
- memset(&tz, 0, sizeof(tz));
+ if (signal(SIGALRM, sighandler) == SIG_ERR) {
+ printf("Some kind of signal failure.\n");
+ return;
+ }
- /* get this function in cached memory */
- gettimeofday(&tvstart, &tz);
cycles[0] = rdtsc();
- gettimeofday(&tvstart, &tz);
- /* we don't trust that this is any specific length of time */
- usleep(250000);
+ alarm(1);
+ while (!nosignal)
+ r = r * rand();
- gettimeofday(&tvstop, &tz);
- cycles[1] = rdtsc();
- gettimeofday(&tvstop, &tz);
+ nosignal = 0;
- microseconds = ((tvstop.tv_sec-tvstart.tv_sec)*1000000) +
- (tvstop.tv_usec-tvstart.tv_usec);
+ cycles[1] = rdtsc();
- cpu->MHz = (int) (cycles[1]-cycles[0]) / (microseconds/freq);
+ cpu->MHz = (cycles[1] - cycles[0]) / 1000000;
if ((cpu->MHz % 50) > 15)
cpu->MHz = ((cpu->MHz / 50) * 50) + 50;
else
cpu->MHz = ((cpu->MHz / 50) * 50);
}
-
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/bench/bench.h
^
|
| @@ -1,21 +1,22 @@
-#define rdtsc() ({ unsigned long a,d; asm volatile("rdtsc":"=a" (a), "=d" (d)); a; })
+static inline unsigned long long int rdtsc(void)
+{
+ unsigned int low, high;
+ unsigned long tsc;
+
+ __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
+ tsc = ((unsigned long long) high << 32) | low;
+ return tsc;
+}
#define NREPS 1000
#define TIME(x,y) \
{ \
- int i,j; \
- unsigned long bmin,bstart,bend; \
- for (j=0; j<100; j++) { \
- bmin = 100000; \
- bstart = rdtsc(); \
- for (i=0; i<NREPS; i++) \
- x; \
- bend = rdtsc(); \
- bend -= bstart; \
- if (bend < bmin) \
- bmin = bend; \
- } \
- printf(y ": %ld cycles\n", bmin/NREPS); \
+ int i; \
+ unsigned long bstart, bend; \
+ bstart = rdtsc(); \
+ for (i=0; i<NREPS; i++) \
+ x; \
+ bend = rdtsc(); \
+ printf(y ": %ld cycles\n", ((bend-bstart)/NREPS)); \
}
-
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/bench/benchmarks.c
^
|
| @@ -9,20 +9,20 @@
#include <asm/unistd.h>
#endif
-void show_benchmarks(void)
+#include <sys/types.h>
+#include <unistd.h>
+
+void show_benchmarks(struct cpudata *cpu __attribute__((unused)))
{
int tmp = 0;
- if (show_bench != 1)
- return;
-
#ifdef __linux__
TIME(asm volatile("int $0x80" :"=a" (tmp) :"0" (__NR_getppid)), "int 0x80");
#endif
TIME(asm volatile("cpuid": : :"ax", "dx", "cx", "bx"), "cpuid");
- TIME(asm volatile("addl $1,0(%esp)"), "addl");
- TIME(asm volatile("lock ; addl $1,0(%esp)"), "locked add");
+ //TIME(asm volatile("addl $1,0(%esp)"), "addl");
+ //TIME(asm volatile("lock ; addl $1,0(%esp)"), "locked add");
TIME(asm volatile("bswap %0" : "=r" (tmp) : "0" (tmp)), "bswap");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/binary.c
^
|
| @@ -1,22 +1,31 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Binary output routines.
+ */
+
#include <stdio.h>
+#include "x86info.h"
-void binary (unsigned int n, unsigned long value)
+void binary(unsigned int n, unsigned long value)
{
unsigned int i;
- for(i=0; i<n; i++, value<<=1)
+ for (i=0; i<n; i++, value<<=1)
(void)putchar( (1<<(n-1) & value) ? '1' : '0' );
(void)putchar('\n');
}
-void binary32 (unsigned long value)
+void binary32(unsigned long value)
{
int i;
- for(i=0;i<32;i++,value<<=1) {
+ for (i=0;i<32;i++,value<<=1) {
(void)putchar( (1<<31 & value) ? '1' : '0' );
- if(i==23 || i==15 || i==7)
+ if (i==23 || i==15 || i==7)
(void)putchar(' ');
}
(void)putchar('\n');
@@ -24,7 +33,7 @@
void binary64(unsigned long long value)
{
- binary32 (value>>32);
- printf (" ");
- binary32 (value);
+ binary32(value>>32);
+ printf(" ");
+ binary32(value);
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/connector.c
^
|
| @@ -1,5 +1,9 @@
/*
- * Decode and print the name of the connector the CPU plugs into.
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Decode and print the name of the connector the CPU plugs into.
*/
#include <stdio.h>
@@ -26,6 +30,7 @@
{CONN_SOCKET_939, "Socket 939"},
{CONN_SOCKET_940, "Socket 940"},
{CONN_SOCKET_S1G1, "Socket S1g1"},
+ {CONN_SOCKET_S1G2, "Socket S1g2"},
{CONN_SOCKET_F, "Socket F (1207)"},
{CONN_SOCKET_AM2, "Socket AM2"},
{CONN_SOCKET_F_R2, "Socket Fr2 (1207)"},
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/cpuid.c
^
|
| @@ -1,12 +1,11 @@
/*
- * $Id: cpuid.c,v 1.12 2005/04/25 20:54:12 davej Exp $
- * This file is part of x86info
- * (C) 2000, 2001 Dave Jones.
- * Fixes by Arjan van de Ven (arjanv@redhat.com) and
- * Philipp Rumpf (prumpf@mandrakesoft.com)
+ * (C) 2000, 2001 Dave Jones.
+ * Fixes by Arjan van de Ven (arjanv@redhat.com) and
+ * Philipp Rumpf (prumpf@mandrakesoft.com)
*
- * Licensed under the terms of the GNU GPL License version 2.
+ * Licensed under the terms of the GNU GPL License version 2.
*
+ * Routines for retrieving cpuid registers.
*/
#define _LARGEFILE64_SOURCE
@@ -20,6 +19,9 @@
#include <unistd.h>
#include <errno.h>
+#define __USE_GNU
+#include <sched.h>
+
#if defined(__FreeBSD__)
# include <sys/ioctl.h>
# include <cpu.h>
@@ -27,12 +29,62 @@
#include "x86info.h"
+/*
+ * sched_* calls weren't stable until 2.3.4
+ * AFAIK, there's no macro to check for the .4, so we just
+ * check for the next minor version up. (2.4)
+ */
+#ifdef __GLIBC__
+#if __GLIBC__ < 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ < 4
+#error Need at least glibc 2.4
+#endif
+#endif
+
+static void native_cpuid(unsigned int cpunr, unsigned long long idx,
+ unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ cpu_set_t set;
+ unsigned int a = 0, b = 0, c = 0, d = 0;
+
+ if (eax != NULL)
+ a = *eax;
+ if (ebx != NULL)
+ b = *ebx;
+ if (ecx != NULL)
+ c = *ecx;
+ if (edx != NULL)
+ d = *edx;
+
+ if (sched_getaffinity(getpid(), sizeof(set), &set) == 0) {
+ CPU_ZERO(&set);
+ CPU_SET(cpunr, &set);
+ sched_setaffinity(getpid(), sizeof(set), &set);
+ }
+
+ asm("cpuid"
+ : "=a" (a),
+ "=b" (b),
+ "+c" (c),
+ "=d" (d)
+ : "0" ((unsigned int)idx));
+
+ if (eax!=NULL)
+ *eax = a;
+ if (ebx!=NULL)
+ *ebx = b;
+ if (ecx!=NULL)
+ *ecx = c;
+ if (edx!=NULL)
+ *edx = d;
+}
+
#if defined(__FreeBSD__)
-void cpuid (int CPU_number, unsigned int idx,
- unsigned long *eax,
- unsigned long *ebx,
- unsigned long *ecx,
- unsigned long *edx)
+void cpuid(unsigned int CPU_number, unsigned long long idx,
+ unsigned int *eax,
+ unsigned int *ebx,
+ unsigned int *ecx,
+ unsigned int *edx)
{
static int nodriver=0;
char cpuname[20];
@@ -40,8 +92,8 @@
int fh;
cpu_cpuid_args_t args;
- if (nodriver==1) {
- cpuid_UP(idx, eax, ebx, ecx, edx);
+ if (nodriver == 1) {
+ native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
return;
}
@@ -68,7 +120,7 @@
if (!silent && nrCPUs != 1)
perror(cpuname);
used_UP = 1;
- cpuid_UP (idx, eax, ebx, ecx, edx);
+ native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
return;
}
}
@@ -80,19 +132,25 @@
*/
#define CPUID_CHUNK_SIZE (16)
-void cpuid (int CPU_number, unsigned int idx,
- unsigned long *eax,
- unsigned long *ebx,
- unsigned long *ecx,
- unsigned long *edx)
+void cpuid(unsigned int CPU_number, unsigned long long idx,
+ unsigned int *eax,
+ unsigned int *ebx,
+ unsigned int *ecx,
+ unsigned int *edx)
{
static int nodriver=0;
char cpuname[20];
unsigned char buffer[CPUID_CHUNK_SIZE];
int fh;
- if (nodriver==1) {
- cpuid_UP(idx, eax, ebx, ecx, edx);
+ if (eax != NULL) {
+ *eax = (unsigned int) idx;
+ if (*eax == 4)
+ *ecx = idx >> 32;
+ }
+
+ if (nodriver == 1) {
+ native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
return;
}
@@ -124,12 +182,16 @@
} else {
/* Something went wrong, just do UP and hope for the best. */
nodriver = 1;
- if (!silent && nrCPUs != 1)
- perror(cpuname);
used_UP = 1;
- cpuid_UP (idx, eax, ebx, ecx, edx);
+ native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
return;
}
}
#endif /* __FreeBSD__ */
+
+void cpuid4(unsigned int CPU_number, unsigned long long idx,
+ unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
+{
+ cpuid(CPU_number, 4 | (idx << 32), eax, ebx, ecx, edx);
+}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/cpuid.h
^
|
| @@ -0,0 +1,11 @@
+#ifndef _CPUID_H
+#define _CPUID_H
+
+extern void cpuid_UP (unsigned int idx, unsigned long *eax, unsigned long *ebx,
+ unsigned long *ecx, unsigned long *edx);
+extern void cpuid(unsigned int cpu, unsigned long long idx, unsigned int *eax,
+ unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
+extern void cpuid4(unsigned int cpu, unsigned long long idx, unsigned int *eax,
+ unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
+
+#endif /* _CPUID_H */
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/dumpregs.c
^
|
| @@ -0,0 +1,21 @@
+/*
+ * (C) 2001,2008 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ */
+
+#include <stdio.h>
+#include "x86info.h"
+
+void dumpregs(int cpunum, unsigned int begin, unsigned int end)
+{
+ unsigned int i;
+ unsigned int eax, ebx, ecx, edx;
+
+ /* Dump all the CPUID results in raw hex */
+ for (i=begin; i<=end; i++) {
+ cpuid(cpunum, i, &eax, &ebx, &ecx, &edx);
+ printf("eax in: 0x%08x, eax = %08x ebx = %08x ecx = %08x edx = %08x\n", i, eax, ebx, ecx, edx);
+ }
+ printf("\n");
+}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/features.c
^
|
| @@ -1,5 +1,4 @@
/*
- * This file is part of x86info
* (C) 2001-2006 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -10,7 +9,7 @@
#include <stdio.h>
#include "x86info.h"
-void flag_decode(unsigned long reg, const char *flags[])
+static void flag_decode(unsigned long reg, const char *flags[])
{
unsigned int i;
@@ -25,9 +24,23 @@
}
-void decode_feature_flags(struct cpudata *cpu)
+void get_feature_flags(struct cpudata *cpu)
{
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
+
+ cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
+ cpu->flags_ecx = ecx;
+ cpu->flags_edx = edx;
+ if (cpu->maxei >= 0x80000001) {
+ cpuid(cpu->number, 0x80000001, &eax, &ebx, &ecx, &edx);
+ cpu->eflags_ecx = ecx;
+ cpu->eflags_edx = edx;
+ }
+}
+
+void show_feature_flags(struct cpudata *cpu)
+{
+ unsigned int eax, ebx, ecx, edx;
unsigned int i;
/* CPUID 0x00000001 EDX flags */
@@ -135,27 +148,15 @@
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
};
- cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
- cpu->flags_ecx = ecx;
- cpu->flags_edx = edx;
- if (cpu->maxei >= 0x80000001) {
- cpuid(cpu->number, 0x80000001, &eax, &ebx, &ecx, &edx);
- cpu->eflags_ecx = ecx;
- cpu->eflags_edx = edx;
- }
-
- if (silent != 0)
- return;
-
- printf ("Feature flags:\n");
+ printf("Feature flags:\n");
for (i=0; i<32; i++) {
if (cpu->flags_edx & (1 << i)) {
if (!(generic_cap_flags_desc[i]))
printf(" [%u]", i);
if (verbose)
- printf ("\t%s\n", generic_cap_flags_desc[i]);
+ printf("\t%s\n", generic_cap_flags_desc[i]);
else
- printf (" %s", generic_cap_flags[i]);
+ printf(" %s", generic_cap_flags[i]);
}
}
@@ -164,20 +165,20 @@
case VENDOR_AMD:
for (i=0; i<32; i++) {
if (cpu->flags_ecx & (1 << i) && amd_cap_generic_ecx_flags[i])
- printf (" %s", amd_cap_generic_ecx_flags[i]);
+ printf(" %s", amd_cap_generic_ecx_flags[i]);
}
printf("\n");
if (cpu->maxei < 0x80000001)
break;
- printf ("Extended feature flags:\n");
+ printf("Extended feature flags:\n");
flag_decode(cpu->eflags_edx, amd_cap_extended_edx_flags);
flag_decode(cpu->eflags_ecx, amd_cap_extended_ecx_flags);
printf("\n");
break;
case VENDOR_CENTAUR:
- printf ("\n");
- printf ("Extended feature flags:\n");
+ printf("\n");
+ printf("Extended feature flags:\n");
flag_decode(cpu->flags_ecx, centaur_cap_extended_ecx_flags);
cpuid(cpu->number, 0xc0000000, &eax, &ebx, &ecx, &edx);
if (eax >=0xc0000001) {
@@ -188,22 +189,22 @@
break;
case VENDOR_TRANSMETA:
- printf ("\n");
- printf ("Extended feature flags:\n");
+ printf("\n");
+ printf("Extended feature flags:\n");
flag_decode(cpu->flags_ecx, transmeta_cap_flags);
break;
case VENDOR_CYRIX:
- printf ("\n");
+ printf("\n");
break;
case VENDOR_INTEL:
- printf ("\n");
- printf ("Extended feature flags:\n");
+ printf("\n");
+ printf("Extended feature flags:\n");
flag_decode(cpu->flags_ecx, intel_cap_generic_ecx_flags);
if (cpu->maxei < 0x80000001)
break;
- printf ("\n");
+ printf("\n");
flag_decode(cpu->eflags_edx, intel_cap_extended_edx_flags);
flag_decode(cpu->eflags_ecx, intel_cap_extended_ecx_flags);
break;
@@ -213,5 +214,5 @@
break;
}
- printf ("\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/generic_msr.regs
^
|
| @@ -0,0 +1,386 @@
+# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+#
+# Copyright (C) 2008 Advanced Micro Devices, Inc.
+
+# This file contains information from:
+# "24593 Rev 3.14 - September 2007, AMD64 Technology - AMD64
+# Architecture Programmer's Manual Volume 2: System Programming"
+# and
+# "The Intel Architecture Software Developer's Manual, Volume 3:
+# System Programing Guide (Order Number 243192)"
+# and
+# "The Intel 64 and IA-32 Architectures Software Developer's Manual:
+# System Programming Guide Part 1, (Order Number 253668),
+# System Programming Guide Part 2, (Order Number 253669)"
+
+
+
+# See scripts/createheader.py for the general format of this register
+# definitions.
+
+{TSC=0x0010;time-stamp counter
+ TSC:64
+}
+
+{APIC_BASE=0x001b;APIC base address
+ :8
+ BSC:1
+ :2
+ ApicEn:1
+ ApicBar:36;;20 for 32-bit, 24 for Intel, 28 for AMD K8, 36 for AMD fam10h
+ :16
+}
+
+{EBL_CR_POWERON=0x002a;cluster ID
+ :16
+ ClusterID:2
+ :46
+}
+
+{MTRRcap=0x00fe;MTRR capabilities
+ MtrrCapVCnt:8
+ MtrrCapFix:1
+ :1
+ MtrrCapWc:1
+ :53
+}
+
+{MCG_CAP=0x0179;global MC capabilities
+ Count:8
+ MCG_CTL_P:1
+ :55
+}
+
+{MCG_STAT=0x017a;global MC status
+ RIPV:1
+ EIPV:1
+ MCIP:1
+ :61
+}
+
+{MCG_CTL=0x017b;global MC control
+ val:64
+}
+
+{DBG_CTL_MSR=0x01d9;debug control
+ LBR:1
+ BTF:1
+ :62
+}
+
+{LastBranchFromIP=0x01db;last branch from IP
+ LastBranchFromIP:64;;32 bits on Intel
+}
+
+{LastBranchToIP=0x01dc;last branch to IP
+ LastBranchToIP:64;;32 bits on Intel
+}
+
+{LastExceptionFromIP=0x01dd;last exception from IP
+ LastExceptionFromIP:64;;32 bits on Intel
+}
+
+{LastExceptionToIP=0x01de;last exception to IP
+ LastExceptionToIP:64;;32 bits on Intel
+}
+
+{MTRRphysBase0=0x0200;base of variable-size MTRR (0)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask0=0x0201;mask of variable-size MTRR (0)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase1=0x0202;base of variable-size MTRR (1)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask1=0x0203;mask of variable-size MTRR (1)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase2=0x0204;base of variable-size MTRR (2)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask2=0x0205;mask of variable-size MTRR (2)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase3=0x0206;base of variable-size MTRR (3)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask3=0x0207;mask of variable-size MTRR (3)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase4=0x0208;base of variable-size MTRR (4)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask4=0x0209;mask of variable-size MTRR (4)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase5=0x020a;base of variable-size MTRR (5)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask5=0x020b;mask of variable-size MTRR (5)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase6=0x020c;base of variable-size MTRR (6)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask6=0x020d;mask of variable-size MTRR (6)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase7=0x020e;base of variable-size MTRR (7)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask7=0x020f;mask of variable-size MTRR (7)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRfix64K_00000=0x0250;fixed range MTRR
+ 0xxxxType:8
+ 1xxxxType:8
+ 2xxxxType:8
+ 3xxxxType:8
+ 4xxxxType:8
+ 5xxxxType:8
+ 6xxxxType:8
+ 7xxxxType:8
+}
+
+{MTRRfix16K_80000=0x0258;fixed range MTRR
+ 80xxxType:8
+ 84xxxType:8
+ 88xxxType:8
+ 8CxxxType:8
+ 90xxxType:8
+ 94xxxType:8
+ 98xxxType:8
+ 9CxxxType:8
+}
+
+{MTRRfix16K_A0000=0x0259;fixed range MTRR
+ A0xxxType:8
+ A4xxxType:8
+ A8xxxType:8
+ ACxxxType:8
+ B0xxxType:8
+ B4xxxType:8
+ B8xxxType:8
+ BCxxxType:8
+}
+
+{MTRRfix4K_C0000=0x0268;fixed range MTRR
+ C0xxxType:8
+ C1xxxType:8
+ C2xxxType:8
+ C3xxxType:8
+ C4xxxType:8
+ C5xxxType:8
+ C6xxxType:8
+ C7xxxType:8
+}
+
+{MTRRfix4K_C8000=0x0269;fixed range MTRR
+ C8xxxType:8
+ C9xxxType:8
+ CAxxxType:8
+ CBxxxType:8
+ CCxxxType:8
+ CDxxxType:8
+ CExxxType:8
+ CFxxxType:8
+}
+
+{MTRRfix4K_D0000=0x026a;fixed range MTRR
+ D0xxxType:8
+ D1xxxType:8
+ D2xxxType:8
+ D3xxxType:8
+ D4xxxType:8
+ D5xxxType:8
+ D6xxxType:8
+ D7xxxType:8
+}
+
+{MTRRfix4K_D8000=0x026b;fixed range MTRR
+ D8xxxType:8
+ D9xxxType:8
+ DAxxxType:8
+ DBxxxType:8
+ DCxxxType:8
+ DDxxxType:8
+ DExxxType:8
+ DFxxxType:8
+}
+
+{MTRRfix4K_E0000=0x026c;fixed range MTRR
+ E0xxxType:8
+ E1xxxType:8
+ E2xxxType:8
+ E3xxxType:8
+ E4xxxType:8
+ E5xxxType:8
+ E6xxxType:8
+ E7xxxType:8
+}
+
+{MTRRfix4K_E8000=0x026d;fixed range MTRR
+ E8xxxType:8
+ E9xxxType:8
+ EAxxxType:8
+ EBxxxType:8
+ ECxxxType:8
+ EDxxxType:8
+ EExxxType:8
+ EFxxxType:8
+}
+
+{MTRRfix4K_F0000=0x026e;fixed range MTRR
+ F0xxxType:8
+ F1xxxType:8
+ F2xxxType:8
+ F3xxxType:8
+ F4xxxType:8
+ F5xxxType:8
+ F6xxxType:8
+ F7xxxType:8
+}
+
+{MTRRfix4K_F8000=0x026f;fixed range MTRR
+ F8xxxType:8
+ F9xxxType:8
+ FAxxxType:8
+ FBxxxType:8
+ FCxxxType:8
+ FDxxxType:8
+ FExxxType:8
+ FFxxxType:8
+}
+
+{PAT=0x0277;page attribute table
+ PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+}
+
+{MTRRdefType=0x02ff;MTRR default memory type
+ MemType:8;;just 3 bits for older 32-bit CPUs
+ :2
+ MtrrDefTypeFixEn:1
+ MtrrDefTypeEn:1
+ :52
+}
+
+{EFER=0xc0000080;extended feature enable
+ SYSCALL:1
+ :7
+ LME:1
+ :1
+ LMA:1
+ NXE:1
+ :52
+} # just for newer CPUs, supporting 64-bit
+
+{STAR=0xc0000081;SYSCALL target address
+ res:32;;target on AMD64
+ SysCallSel:16
+ SysRetSel:16
+} # just for newer CPUs, supporting 64-bit
+
+{LSTAR=0xc0000082;long mode SYSCALL target address
+ LSTAR:64
+} # just for newer CPUs, supporting 64-bit
+
+{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask
+ MASK:32
+ :32
+}
+
+{FS_BASE=0xc0000100;FS base
+ FS_BASE:64
+}
+
+{GS_BASE=0xc0000101;GS base
+ GS_BASE:64
+}
+
+{KernelGSbase=0xc0000102;kernel GS base
+ KernelGSBase:64
+}
+
+### Local Variables: ###
+### mode:shell-script ###
+### End: ###
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/get_model_name.c
^
|
| @@ -1,12 +1,9 @@
/*
- * $Id: get_model_name.c,v 1.4 2003/06/13 11:36:20 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Get CPU name string from cpuid.
- *
*/
#include <stdio.h>
@@ -16,7 +13,7 @@
void get_model_name(struct cpudata *cpu)
{
unsigned int i, j;
- unsigned long eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx;
char namestring[49], *cp;
if (cpu->maxei < 0x80000004)
@@ -43,10 +40,10 @@
/* Broken BIOS? Try to determine the model name ourselves. */
if (strstr(cp, "unknown") != NULL) {
- unsigned long vendor;
+ unsigned int vendor;
cpuid(cpu->number, 0, NULL, &vendor, NULL, NULL);
if (vendor == 0x68747541 && cpu->maxi >= 1 && cpu->maxei >= 0x80000001) { /* AMD defined flags */
- unsigned long bid, ebid;
+ unsigned int bid, ebid;
cpuid(cpu->number, 0x00000001, NULL, &bid, NULL, NULL);
bid &= 0xff;
cpuid(cpu->number, 0x80000001, NULL, &ebid, NULL, NULL);
@@ -128,5 +125,5 @@
}
}
- printf("Processor name string: %s\n\n", cp);
+ printf("Processor name string: %s\n", cp);
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/havecpuid.c
^
|
| @@ -1,6 +1,13 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ */
+
#include <stdio.h>
+#include "x86info.h"
-static __inline__ int flag_is_changeable_p(unsigned long flag)
+static int flag_is_changeable_p(unsigned long flag)
{
unsigned long f1, f2;
__asm__ volatile("pushf\n\t"
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/identify.c
^
|
| @@ -1,22 +1,28 @@
/*
- * $Id: identify.c,v 1.28 2003/11/04 02:02:43 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
- *
*/
#include <stdio.h>
#include "x86info.h"
-void identify(struct cpudata *cpu)
+void get_cpu_info_basics(struct cpudata *cpu)
{
- unsigned long maxi, maxei, vendor;
+ unsigned int maxi, maxei, vendor;
+ unsigned int eax;
cpuid(cpu->number, 0, &maxi, &vendor, NULL, NULL);
maxi &= 0xffff; /* The high-order word is non-zero on some Cyrix CPUs */
cpu->maxi = maxi;
+ if (cpu->maxi < 1)
+ return;
+
+ /* Everything that supports cpuid supports these. */
+ cpuid(cpu->number, 1, &eax, NULL, NULL, NULL);
+ cpu->stepping = eax & 0xf;
+ cpu->model = (eax >> 4) & 0xf;
+ cpu->family = (eax >> 8) & 0xf;
cpuid(cpu->number, 0x80000000, &maxei, NULL, NULL, NULL);
cpu->maxei = maxei;
@@ -25,45 +31,62 @@
cpu->maxei2 = maxei;
switch (vendor) {
- case 0x756e6547: /* Intel */
- Identify_Intel(cpu);
+ case 0x756e6547:
+ cpu->vendor = VENDOR_INTEL;
break;
- case 0x68747541: /* AMD */
- Identify_AMD(cpu);
+ case 0x68747541:
+ cpu->vendor = VENDOR_AMD;
break;
- case 0x69727943: /* Cyrix */
- Identify_Cyrix(cpu);
+ case 0x69727943:
+ cpu->vendor = VENDOR_CYRIX;
break;
- case 0x746e6543: /* IDT */
- Identify_IDT(cpu);
+ case 0x746e6543:
+ cpu->vendor = VENDOR_CENTAUR;
break;
- case 0x646f6547: /* Natsemi Geode */
- Identify_NatSemi(cpu);
+ case 0x646f6547:
+ cpu->vendor = VENDOR_NATSEMI;
break;
- case 0x52697365: /* Rise This should be checked. Why 2 ? */
- case 0x65736952: /* Rise */
- Identify_RiSE(cpu);
+ case 0x52697365:
+ case 0x65736952:
+ cpu->vendor = VENDOR_RISE;
break;
- case 0x20536953: /* SiS */
- Identify_SiS(cpu);
+ case 0x20536953:
+ cpu->vendor = VENDOR_SIS;
break;
default:
- printf("Unknown vendor (%lx)\n", vendor);
+ printf("Unknown vendor (%x)\n", vendor);
return;
}
}
-static void dumpregs (int cpunum, unsigned int begin, unsigned int end)
+void identify(struct cpudata *cpu)
{
- unsigned int i;
- unsigned long eax, ebx, ecx, edx;
-
- /* Dump all the CPUID results in raw hex */
- for (i=begin; i<=end; i++) {
- cpuid (cpunum, i, &eax, &ebx, &ecx, &edx);
- printf ("eax in: 0x%08x, eax = %08lx ebx = %08lx ecx = %08lx edx = %08lx\n", i, eax, ebx, ecx, edx);
+ switch (cpu->vendor) {
+ case VENDOR_INTEL:
+ Identify_Intel(cpu);
+ break;
+ case VENDOR_AMD:
+ Identify_AMD(cpu);
+ break;
+ case VENDOR_CYRIX:
+ Identify_Cyrix(cpu);
+ break;
+ case VENDOR_CENTAUR:
+ identify_centaur(cpu);
+ break;
+ case VENDOR_NATSEMI:
+ identify_natsemi(cpu);
+ break;
+ case VENDOR_RISE:
+ identify_RiSE(cpu);
+ break;
+ case VENDOR_SIS:
+ identify_sis(cpu);
+ break;
+ case VENDOR_TRANSMETA:
+ case VENDOR_UNKNOWN:
+ break;
}
- printf ("\n");
}
void show_info(struct cpudata *cpu)
@@ -71,14 +94,12 @@
if (silent)
return;
- if (show_registers) {
- dumpregs (cpu->number, 0, cpu->maxi);
- if (cpu->maxei >=0x80000000)
- dumpregs (cpu->number, 0x80000000, cpu->maxei);
+ printf("EFamily: %u EModel: %u Family: %u Model: %u Stepping: %u\n",
+ cpu->efamily, cpu->emodel, cpu->family,
+ model(cpu), cpu->stepping);
+ printf("CPU Model: %s\n", cpu->name);
- if (cpu->maxei2 >=0xC0000000)
- dumpregs (cpu->number, 0xC0000000, cpu->maxei2);
- }
+ get_model_name(cpu);
switch (cpu->vendor) {
case VENDOR_AMD:
@@ -90,46 +111,14 @@
break;
case VENDOR_CENTAUR:
- display_IDT_info(cpu);
+ display_centaur_info(cpu);
break;
case VENDOR_INTEL:
display_Intel_info(cpu);
break;
- case VENDOR_NATSEMI:
- display_NatSemi_info(cpu);
- break;
-
- case VENDOR_RISE:
- display_RiSE_info(cpu);
- break;
-
- case VENDOR_SIS:
- display_SiS_info(cpu);
- break;
-
default:
break;
}
-
- if (show_connector)
- decode_connector (cpu->connector);
-
- if (show_urls) {
- if (cpu->datasheet_url != NULL)
- printf ("Datasheet: %s\n", cpu->datasheet_url);
-
- if (cpu->errata_url != NULL)
- printf ("Errata: %s\n", cpu->errata_url);
-
- printf ("\n");
- }
-
- if (!user_is_root)
- return;
-
- if (show_mtrr)
- dump_mtrrs(cpu);
}
-
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/lsmsr.8
^
|
| @@ -0,0 +1,146 @@
+.\" Copyright (C) 2008 Advanced Micro Devices, Inc.
+'\"! tbl | mmdoc
+'\"macro stdmacro
+.nr X
+.TH lsmsr 8 "July 2008" "x86utils"
+.SH NAME
+lsmsr \- show MSR information for x86 CPUs
+
+.SH SYNOPSIS
+.B lsmsr
+.RB [ \-hv ]
+.RB [ \-a
+.RB [ \-c
+.IR cpu_nr ]
+.RB [ \-f
+.IR family ]
+.RB [ \-l]
+.RB [ \-r
+.IR name|address ]
+.RB [\-V
+.IR verbosity]
+.IR [MSR]
+
+.SH DESCRIPTION
+.PP
+.B lsmsr
+is a tool to display information for machine specific registers
+of x86 CPUs. Following CPUs are supported:
+AMD family 0xf and family 0x10. For Intel and other AMD CPUs just
+a some common MSRs is supported.
+.SH OPTIONS
+.TP
+.B -a, --all
+Show information for all MSRs known to the tool for that CPU family.
+.TP
+.B -c cpu_nr, --cpu cpu_nr
+Select CPU (by number) for which MSR information should be displayed
+(default: 0).
+.TP
+.B -f fam, --family fam
+Specify CPU family. Normally CPU family is auto-detected. You can
+use this option to disable auto-detection, e.g. for debugging
+purposes.
+.TP
+.B -l, --list
+Show definition (address, field description) of selected MSR(s).
+.TP
+.B -r name|address, --register name|address
+Specify MSR (by name or address in hex) for which MSR information
+should be displayed.
+.TP
+.B -V num, --verbosity num
+Select verbosity of output format (between 0 and 4, default: 0)
+.TP
+.B -h, --help
+Print help message and exit.
+.TP
+.B -v, --version
+Display version info and exit.
+.SH Examples
+.IP "" 0
+Show all MSRs beginning with 'MTRR' and force CPU family to 0x10
+.IP "" 2
+# lsmsr -l -f 0x10 MTRR
+ MTRRcap : 0x000000fe
+ MTRRphysBase0 : 0x00000200
+ MTRRphysMask0 : 0x00000201
+ MTRRphysBase1 : 0x00000202
+ MTRRphysMask1 : 0x00000203
+ MTRRphysBase2 : 0x00000204
+ MTRRphysMask2 : 0x00000205
+ MTRRphysBase3 : 0x00000206
+ MTRRphysMask3 : 0x00000207
+ MTRRphysBase4 : 0x00000208
+ MTRRphysMask4 : 0x00000209
+ MTRRphysBase5 : 0x0000020a
+ MTRRphysMask5 : 0x0000020b
+ MTRRphysBase6 : 0x0000020c
+ MTRRphysMask6 : 0x0000020d
+ MTRRphysBase7 : 0x0000020e
+ MTRRphysMask7 : 0x0000020f
+ MTRRfix64K_00000 : 0x00000250
+ MTRRfix16K_80000 : 0x00000258
+ MTRRfix16K_A0000 : 0x00000259
+ MTRRfix4K_C0000 : 0x00000268
+ MTRRfix4K_C8000 : 0x00000269
+ MTRRfix4K_D0000 : 0x0000026a
+ MTRRfix4K_D8000 : 0x0000026b
+ MTRRfix4K_E0000 : 0x0000026c
+ MTRRfix4K_E8000 : 0x0000026d
+ MTRRfix4K_F0000 : 0x0000026e
+ MTRRfix4K_F8000 : 0x0000026f
+ MTRRdefType : 0x000002ff
+.IP ""0
+Show 'MTRRcap MSR in verbose one-line mode
+.IP "" 2
+# lsmsr -r MTRRcap -V 1
+ MTRRcap = 0x0000000000000508 (MtrrCapVCnt=0x8, MtrrCapFix=0x1, MtrrCapWc=0x1)
+.IP "" 0
+Show 'MTRRdefType' in verbose multi-line mode
+.IP "" 2
+# lsmsr -r MTRRdefType -V 3
+ MTRRdefType = 0x0000000000000c00
+ MtrrDefMemType=0
+ MtrrDefTypeFixEn=0x1
+ MtrrDefTypeEn=0x1
+.IP "" 0
+Show definition of MSR 0x200 in verbose multi-line mode (including reserved fields)
+.IP "" 2
+# lsmsr -r 0x200 -V 4 -l
+ MTRRphysBase0: 0x00000200
+ 0-7:Type
+ 8-11:res
+ 12-39:PhyBase
+ 40-63:res
+.IP "" 0
+List all known MSRs for family 0xf
+.IP "" 2
+# lsmsr -f 0xf -l -a
+ TSC : 0x00000010; time-stamp counter
+ APIC_BASE : 0x0000001b; APIC base address
+
+ ...
+
+ MTRRphysBase0 : 0x00000200; base of variable MTRR (0)
+ MTRRphysMask0 : 0x00000201; mask of variable MTRR (0)
+ MTRRphysBase1 : 0x00000202; base of variable MTRR (1)
+ MTRRphysMask1 : 0x00000203; mask of variable MTRR (1)
+
+ ...
+
+ MTRRfix4K_F0000 : 0x0000026e
+ MTRRfix4K_F8000 : 0x0000026f
+ PAT : 0x00000277; page attribute table
+ MTRRdefType : 0x000002ff
+
+
+.SH Author
+.B lsmsr
+and this manual page was written by Andreas Herrmann <andreas.herrman3@amd.com>.
+.PP
+Permission is granted to copy, distribute and/or modify this
+document under the terms of the GNU General Public License version 2.
+
+.SH REPORTING BUGS
+Please send bug reports to <andreas.herrmann3@amd.com>.
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/lsmsr.c
^
|
| @@ -0,0 +1,409 @@
+/*
+ * Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2.
+ * See file COPYING for details.
+ */
+
+#define _LARGEFILE64_SOURCE
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <ctype.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE
+#endif
+#include <getopt.h>
+
+#include "msr.h"
+#include "cpuid.h"
+#include "x86info.h"
+#include "AMD/k8.h"
+#include "AMD/fam10h.h"
+#include "generic_msr.h"
+
+/* Todos:
+ * - add (list and eventually write) support for write-only MSR
+ * - add decoding support for bit fields
+ * - proper check for MSR support
+ * - add support for generic MSRs for non-Intel/AMD CPUs
+ */
+
+#define VERSION "0.815"
+
+struct {
+ int fd;
+ int show_all;
+ int list;
+ int verbosity;
+ int cpu;
+ enum vendor vendor;
+ int family;
+ int model;
+ struct reg_spec *msr_table;
+ const char *prog;
+ const char *msr_name;
+ const char *msr_search;
+ uint32_t reg;
+} g = {
+ .reg = -1,
+};
+
+int used_UP = 0;
+
+/* getopt_long stuff */
+static struct option lopts[] = {
+ {"all", no_argument, 0, 'a'}, /* show all MSRs */
+ {"cpu", required_argument, 0, 'c'}, /* CPU number */
+ {"family", required_argument, 0, 'f'}, /* CPU family */
+ {"list", no_argument, 0, 'l'}, /* list known MSRs */
+ {"register", required_argument, 0, 'r'}, /* register name or address */
+ {"help", no_argument, 0, 'h'}, /* help */
+ {"model", required_argument, 0, 'm'}, /* CPU model */
+ {"version", no_argument, 0, 'v'}, /* version info */
+ {"verbosity", required_argument, 0, 'V'}, /* verbosity */
+ {0, 0, 0, 0}
+};
+
+#define OPTSTRING "ac:C:f:hlm:r:vV:"
+
+#define _USAGE "[OPTION] <MSR>\n"
+
+#define _HELP \
+" -a, --all show info for all known MSRs\n"\
+" -c, --cpu <CPU> specify CPU for which MSRs are shown (default 0)\n"\
+" -f, --family <cpu family> set cpu family to be used\n"\
+" -l, --list list info about MSR(s), its addresses and fields\n"\
+" -r, --register <name|addr> select register by name or address\n"\
+" -h, --help show help\n"\
+" -m, --model set cpu model to be used\n"\
+" -v, --version show version info\n"\
+" -V, --verbosity <n> set verbosity\n"\
+" V=1 show all fields of the register\n"\
+" V=2 dito and show reserved fields\n"\
+" V=3 like V=1 but each field on separate line\n"\
+" V=4 dito and show reserved fields\n"\
+"\n"\
+" Display model specific registers on AMD64 processors.\n"\
+" If <MSR> is given information for all MSRs for which <MSR> matches the\n"\
+" beginning of its name are displayed. Precedence of MSR selection is:\n"\
+" \" -r <name|addr>\" overrules \"<MSR>\" overrules \"-a\".\n"\
+"\n"
+
+static void usage(void)
+{
+ fprintf(stderr, "Usage: %s "_USAGE, g.prog);
+ fprintf(stderr, "Try '%s --help' for more information\n", g.prog);
+ exit(1);
+}
+
+static void help(void)
+{
+ fprintf(stdout, "Usage: %s "_USAGE, g.prog);
+ fprintf(stdout, "Help:\n"_HELP);
+}
+
+static void version(void)
+{
+ fprintf(stdout, "%s version %s\n", g.prog, VERSION);
+}
+
+static int get_msr_val(unsigned int msr, unsigned long long *val)
+{
+ off64_t off;
+ int err;
+
+ *val = 0;
+ off = lseek64(g.fd, (off64_t) msr, SEEK_SET);
+ if (off == (off_t) -1) {
+ perror("invalid MSR");
+ return 1;
+ }
+
+ off = read(g.fd, val, 8);
+ err = errno;
+ if (off != 8) {
+ fflush(stdout);
+ fprintf(stderr,
+ "could not read MSR 0x%8.8x (%s): %s\n",
+ msr, get_reg_name(msr, g.msr_table), strerror(err));
+ return 0;
+ }
+
+ return 0;
+}
+
+static int open_dev(int cpu)
+{
+ char s[20];
+
+ snprintf(s, sizeof(s), "/dev/cpu/%d/msr", cpu);
+ g.fd = open(s, O_RDONLY);
+ if (g.fd < 0)
+ fprintf(stderr, "could not open device %s: %s\n", s,
+ strerror(errno));
+
+ return g.fd;
+}
+
+#define PRINT_MSR(reg, val) \
+do { \
+ print_reg(reg, val, g.list, g.show_all, g.verbosity); \
+} while(0)
+
+static int _show_msr(struct reg_spec *reg)
+{
+ unsigned long long val;
+ if (!g.list)
+ if (get_msr_val(reg->address, &val))
+ return 1;
+ PRINT_MSR(reg, val);
+ return 0;
+}
+
+static int show_matching(const char *name)
+{
+ int i, t;
+ int n = MSR_MAX_LEN;
+ int ret = 0;
+
+ t = strlen(name);
+ if (t<n)
+ n = t;
+
+ g.show_all = 1;
+ for (i = 0; g.msr_table[i].name; i++) {
+ t = strlen(g.msr_table[i].name);
+ if (n<t)
+ t = n;
+ if (strncmp(name, g.msr_table[i].name, t) == 0)
+ if (_show_msr(&(g.msr_table[i]))) {
+ ret = 1;
+ break;
+ }
+ }
+ g.show_all = 0;
+ return ret;
+}
+
+struct vendor_string {
+ enum vendor id;
+ const char *name;
+} vendor_names[] = {
+ {VENDOR_UNKNOWN, "(unknown)"},
+ {VENDOR_AMD, "AMD"},
+ {VENDOR_CENTAUR, "Centaur"},
+ {VENDOR_CYRIX, "Cyrix"},
+ {VENDOR_INTEL, "Intel"},
+ {VENDOR_NATSEMI, "Natsemi"},
+ {VENDOR_RISE, "Rise"},
+ {VENDOR_TRANSMETA, "Transmeta"},
+ {VENDOR_SIS, "SIS"},
+};
+get_name(vendor, enum vendor, vendor_names);
+
+static void set_vendor(void)
+{
+ unsigned int b;
+ cpuid(g.cpu, 0, NULL, &b, NULL, NULL);
+
+ switch (b) {
+ case 0x68747541:
+ g.vendor = VENDOR_AMD;
+ break;
+ case 0x756e6547:
+ g.vendor = VENDOR_INTEL;
+ break;
+ case 0x69727943:
+ g.vendor = VENDOR_CYRIX;
+ break;
+ case 0x746e6543:
+ g.vendor = VENDOR_CENTAUR;
+ break;
+ case 0x646f6547:
+ g.vendor = VENDOR_NATSEMI;
+ break;
+ case 0x52697365:
+ case 0x65736952:
+ g.vendor = VENDOR_RISE;
+ break;
+ case 0x20536953:
+ g.vendor = VENDOR_SIS;
+ break;
+ default:
+ g.vendor = VENDOR_UNKNOWN;
+ break;
+ }
+}
+
+static void set_family_model(void)
+{
+ unsigned int a;
+ cpuid(g.cpu, 0, &a, NULL, NULL, NULL);
+ if (!g.family) {
+ cpuid(g.cpu, 1, &a, NULL, NULL, NULL);
+ g.family = (a >> 8) & 0xf;
+ if (g.family == 0xf)
+ g.family += (a >> 20) & 0xff;
+ }
+
+ if (!g.model) {
+ cpuid(g.cpu, 1, &a, NULL, NULL, NULL);
+ g.model = (a >> 4) & 0xf;
+ if (g.model == 0xf)
+ g.model |= (a >> 12) & 0xf0;
+ }
+}
+
+static int set_msr_table(void)
+{
+ int supported = 0;
+
+ set_vendor();
+ set_family_model();
+
+ if (g.vendor == VENDOR_AMD) {
+ supported = 1;
+ switch (g.family) {
+ case 0x0f:
+ g.msr_table = k8_spec;
+ break;
+ case 0x10:
+ g.msr_table = fam10h_spec;
+ break;
+ default:
+ g.msr_table = generic_msr_spec;
+ }
+ }
+
+ if (g.vendor == VENDOR_INTEL) {
+ supported = 1;
+ g.msr_table = generic_msr_spec;
+ }
+
+ if (!supported) {
+ fprintf(stdout, "CPU not (yet) supported "
+ "(vendor=\"%s\", family=%d, model=%d)\n",
+ get_vendor_name(g.vendor), g.family, g.model);
+ return 1;
+ }
+
+ return 0;
+}
+
+#define OPT_MAX 32
+int main(int argc, char *argv[])
+{
+ char c;
+ int i, li, ret;
+ struct reg_spec *reg;
+
+ ret = 1;
+ if((g.prog = rindex(argv[0], '/')))
+ ++g.prog;
+ else
+ g.prog = argv[0];
+
+ if (!HaveCPUID()) {
+ fprintf(stderr, "warning: no cpuid instruction available\n");
+ fprintf(stdout, "no MSR information available for this CPU\n");
+ return 0;
+ }
+
+ while((c = getopt_long(argc, argv, OPTSTRING, lopts, &li)) != -1) {
+ switch (c) {
+ case 'a':
+ g.show_all = 1;
+ break;
+ case 'h':
+ help();
+ return 0;
+ case 'v':
+ version();
+ return 0;
+ case 'V':
+ g.verbosity = strtol(optarg, NULL, 10);
+ break;
+ case 'c':
+ g.cpu = strtol(optarg, NULL, 0);
+ break;
+ case 'm':
+ g.model = strtol(optarg, NULL, 0);
+ break;
+ case 'f':
+ g.family = strtol(optarg, NULL, 0);
+ break;
+ case 'l':
+ g.list = 1;
+ break;
+ case 'r':
+ if (isalpha(*optarg))
+ g.msr_name = optarg;
+ else
+ g.reg = (unsigned int) strtol(optarg, NULL, 16);
+ break;
+ default:
+ usage();
+ }
+ }
+
+ if((optind > -1) && argv[optind]) {
+ if ((argc - optind) != 1)
+ usage();
+ if (strlen(argv[optind]) >= OPT_MAX) {
+ fprintf(stderr,"error: invlalid command line\n");
+ goto out;
+ }
+ g.msr_search = argv[optind];
+ }
+
+ if (set_msr_table())
+ goto out;
+
+ if (g.msr_name) {
+ g.reg = get_reg_addr(g.msr_name, g.msr_table);
+ if (g.reg == (uint32_t) -1) {
+ fflush(stdout);
+ fprintf(stderr, "error: unknown register \"%s\"\n",
+ g.msr_name);
+ goto out;
+ }
+ }
+
+ if (!g.list)
+ if(open_dev(g.cpu) < 0)
+ goto out;
+
+ if (g.reg != (uint32_t) -1) {
+ reg = get_reg_spec(g.reg, g.msr_table);
+ if (!reg) {
+ fflush(stdout);
+ fprintf(stderr, "error: unknown MSR %x\n", g.reg);
+ goto out;
+ }
+ if (_show_msr(reg))
+ goto out;
+ } else if (g.msr_search) {
+ if (show_matching(g.msr_search))
+ goto out;
+ } else if (g.show_all) {
+ for (i = 0; g.msr_table[i].name; i++)
+ if (_show_msr(&(g.msr_table[i])))
+ goto out;
+ }
+ ret = 0;
+
+ out:
+ if (g.fd >=0)
+ close(g.fd);
+ return ret;
+}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/mptable.c
^
|
| @@ -23,8 +23,6 @@
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
- *
- * $Id: mptable.c,v 1.8 2005/04/25 20:54:12 davej Exp $
*/
@@ -49,20 +47,20 @@
#define DEFAULT_TOPOFMEM 0xa0000
-#define BIOS_BASE 0xf0000
-#define BIOS_BASE2 0xe0000
-#define BIOS_SIZE 0x10000
-#define ONE_KBYTE 1024
-
-#define GROPE_AREA1 0x80000
-#define GROPE_AREA2 0x90000
-#define GROPE_SIZE 0x10000
-
-#define PROCENTRY_FLAG_EN 0x01
-#define PROCENTRY_FLAG_BP 0x02
-#define IOAPICENTRY_FLAG_EN 0x01
+#define BIOS_BASE 0xf0000
+#define BIOS_BASE2 0xe0000
+#define BIOS_SIZE 0x10000
+#define ONE_KBYTE 1024
+
+#define GROPE_AREA1 0x80000
+#define GROPE_AREA2 0x90000
+#define GROPE_SIZE 0x10000
+
+#define PROCENTRY_FLAG_EN 0x01
+#define PROCENTRY_FLAG_BP 0x02
+#define IOAPICENTRY_FLAG_EN 0x01
-#define MAXPNSTR 132
+#define MAXPNSTR 132
/* global data */
static int pfd; /* physical /dev/mem fd */
@@ -94,7 +92,7 @@
/* MP Floating Pointer Structure */
typedef struct MPFPS {
char signature[4];
- u32 pap;
+ u32 pap;
u8 length;
u8 spec_rev;
u8 checksum;
@@ -113,7 +111,7 @@
u8 checksum;
u8 oem_id[8];
u8 product_id[12];
- u32 oem_table_pointer;
+ u32 oem_table_pointer;
u16 oem_table_size;
u16 entry_count;
u32 apic_address;
@@ -202,7 +200,7 @@
static int MPConfigTableHeader(u32 pap)
{
vm_offset_t paddr;
- mpcth_t cth;
+ mpcth_t cth;
int x;
int totalSize, t;
int count, c;
@@ -240,7 +238,7 @@
totalSize -= basetableEntryTypes[ 0 ].length;
}
if (verbose_mp)
- printf ("\n");
+ printf("\n");
return SMP_YES;
}
@@ -278,7 +276,7 @@
/* read CMOS for real top of mem */
seekEntry((vm_offset_t)TOPOFMEM_POINTER);
readEntry(&segment, 2);
- --segment; /* less ONE_KBYTE */
+ --segment; /* less ONE_KBYTE */
target = segment * 1024;
seekEntry(target);
readEntry(buffer, ONE_KBYTE);
@@ -411,9 +409,9 @@
#ifdef STANDALONE
int main()
{
- int numcpu, smp;
+ int numcpu, smp;
numcpu = enumerate_cpus();
- smp=issmp(1);
+ smp = issmp(1);
printf("SMP: %d\nCPU: %d\n", smp, numcpu);
return 0;
}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/msr.h
^
|
| @@ -0,0 +1,134 @@
+/*
+ * Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2.
+ * See file COPYING for details.
+ */
+
+#ifndef _msr_h
+#define _msr_h
+
+
+#define _RANGE(name, args...) \
+unsigned char name##_range[] = { args }
+
+#define _NAMES(name, args...) \
+const char *name##_spec[] = { args }
+
+#define _SPEC(addr, name, desc, prefix) \
+{addr, #name, desc, prefix##name##_range, prefix##name##_spec}
+
+#define MSR_MAX_LEN 32
+struct reg_spec {
+ unsigned int address;
+ const char *name;
+ const char *desc;
+ unsigned char *bits;
+ const char **spec;
+};
+
+static struct reg_spec *get_reg_spec(uint32_t msr, struct reg_spec *table)
+{
+ int i;
+ for (i = 0; table[i].name; i++)
+ if (msr == table[i].address)
+ return &(table[i]);
+ return NULL;
+}
+
+static uint32_t get_reg_addr(const char *name, struct reg_spec *table)
+{
+ int i;
+
+ for (i = 0; table[i].name; i++)
+ if (strcmp(name, table[i].name) == 0)
+ return table[i].address;
+
+ return -1;
+}
+
+static const char *get_reg_name(uint32_t reg, struct reg_spec *table)
+{
+ struct reg_spec *d;
+ const char *s = NULL;
+
+ d = get_reg_spec(reg, table);
+ if (d)
+ s = d->name;
+
+ return s;
+}
+
+static void print_reg_bits(struct reg_spec *reg, uint64_t val, uint8_t list,
+ uint8_t verb)
+{
+ unsigned char *r;
+ const char **d;
+ int i, j, k;
+ int first, any;
+ uint64_t t;
+ const char *s;
+
+ if (!reg || !reg->bits || !reg->spec)
+ return;
+
+ any = 0;
+ first = 1;
+ r = reg->bits;
+ d = reg->spec;
+ for (i = 0, j = 0; r[i]; i++, j = k + 1){
+ k = j + r[i] - 1;
+ if (d[i] == 0) {
+ if (verb == 2 || verb == 4)
+ s = "res";
+ else /* hide reserved fields */
+ continue;
+ } else
+ s = d[i];
+
+ if (verb > 2)
+ fprintf(stdout, "\n ");
+ else
+ fprintf(stdout, "%s", first ? " (" : ", ");
+
+ if (list)
+ printf("%d-%d:%s", j, k, s);
+ else {
+ if (r[i] == 64)
+ t = val;
+ else
+ t = (val >> j) & ((1ULL<<r[i]) - 1);
+
+ fprintf(stdout, "%s=%#llx", s, (unsigned long long) t);
+ }
+ first = 0;
+ any = 1;
+ }
+ if (any && verb <= 2)
+ fprintf(stdout, ")");
+}
+
+static void print_reg(struct reg_spec *reg, uint64_t val, uint8_t list,
+ uint8_t all, uint8_t verb)
+{
+ if (list) {
+ if ((verb == 0 || verb == 3 || verb ==4) && reg->desc)
+ fprintf(stdout, "%-*s: 0x%8.8x; %s", all ? 20 : 0,
+ reg->name, reg->address, reg->desc);
+ else
+ fprintf(stdout, "%-*s: 0x%8.8x", all ? 20 : 0,
+ reg->name, reg->address);
+
+ } else
+ fprintf(stdout, "%-*s = 0x%16.16llx", all ? 20 : 0,
+ reg->name, (unsigned long long) val);
+
+ if (verb)
+ print_reg_bits(reg, val, list, verb);
+
+ fprintf(stdout, "\n");
+}
+
+#endif /* _msr_h */
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/mtrr.c
^
|
| @@ -1,6 +1,4 @@
/*
- * $Id: mtrr.c,v 1.4 2002/10/30 03:18:07 davej Exp $
- * This file is part of x86info
* (C) 2002 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
@@ -12,57 +10,57 @@
#include <stdio.h>
#include "x86info.h"
-static void dump_mtrr (int cpu, int msr)
+static void dump_mtrr(int cpu, int msr)
{
unsigned long long val=0;
if (read_msr(cpu, msr, &val) == 1)
- printf ("0x%016llx\n", val);
+ printf("0x%016llx\n", val);
}
-void dump_mtrrs (struct cpudata *cpu)
+void dump_mtrrs(struct cpudata *cpu)
{
unsigned int i;
if (!(cpu->flags_edx & (X86_FEATURE_MTRR)))
return;
- printf ("MTRR registers:\n");
+ printf("MTRR registers:\n");
- printf ("MTRRcap (0xfe): ");
- dump_mtrr (cpu->number, 0xfe);
+ printf("MTRRcap (0xfe): ");
+ dump_mtrr(cpu->number, 0xfe);
for (i=0; i<16; i+=2) {
- printf ("MTRRphysBase%u (0x%x): ", i/2, (unsigned int) 0x200+i);
+ printf("MTRRphysBase%u (0x%x): ", i/2, (unsigned int) 0x200+i);
dump_mtrr(cpu->number, 0x200+i);
- printf ("MTRRphysMask%u (0x%x): ", i/2, (unsigned int) 0x201+i);
+ printf("MTRRphysMask%u (0x%x): ", i/2, (unsigned int) 0x201+i);
dump_mtrr(cpu->number, 0x201+i);
}
- printf ("MTRRfix64K_00000 (0x250): ");
+ printf("MTRRfix64K_00000 (0x250): ");
dump_mtrr (cpu->number, 0x250);
- printf ("MTRRfix16K_80000 (0x258): ");
+ printf("MTRRfix16K_80000 (0x258): ");
dump_mtrr (cpu->number, 0x258);
- printf ("MTRRfix16K_A0000 (0x259): ");
+ printf("MTRRfix16K_A0000 (0x259): ");
dump_mtrr (cpu->number, 0x259);
- printf ("MTRRfix4K_C8000 (0x269): ");
+ printf("MTRRfix4K_C8000 (0x269): ");
dump_mtrr (cpu->number, 0x269);
- printf ("MTRRfix4K_D0000 0x26a: ");
+ printf("MTRRfix4K_D0000 0x26a: ");
dump_mtrr (cpu->number, 0x26a);
- printf ("MTRRfix4K_D8000 0x26b: ");
+ printf("MTRRfix4K_D8000 0x26b: ");
dump_mtrr (cpu->number, 0x26b);
- printf ("MTRRfix4K_E0000 0x26c: ");
+ printf("MTRRfix4K_E0000 0x26c: ");
dump_mtrr (cpu->number, 0x26c);
- printf ("MTRRfix4K_E8000 0x26d: ");
+ printf("MTRRfix4K_E8000 0x26d: ");
dump_mtrr (cpu->number, 0x26d);
- printf ("MTRRfix4K_F0000 0x26e: ");
+ printf("MTRRfix4K_F0000 0x26e: ");
dump_mtrr (cpu->number, 0x26e);
- printf ("MTRRfix4K_F8000 0x26f: ");
+ printf("MTRRfix4K_F8000 0x26f: ");
dump_mtrr (cpu->number, 0x26f);
- printf ("MTRRdefType (0x2ff): ");
+ printf("MTRRdefType (0x2ff): ");
dump_mtrr (cpu->number, 0x2ff);
- printf ("\n\n");
+ printf("\n\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/rdmsr.c
^
|
| @@ -1,11 +1,11 @@
/*
- * $Id: rdmsr.c,v 1.16 2003/06/09 22:15:20 davej Exp $
- * This file is part of x86info.
* (C) 2001 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Contributions by Arjan van de Ven & Philipp Rumpf.
+ *
+ * Routines for reading MSRs.
*/
#include <stdio.h>
@@ -17,7 +17,7 @@
#include "x86info.h"
#if defined(__FreeBSD__)
-# include <sys/ioctl.h>
+# include <sys/ioctl.h>
# include <cpu.h>
#endif
@@ -45,17 +45,17 @@
return 0;
}
- args.msr = idx;
- if (ioctl(fh, CPU_RDMSR, &args) != 0) {
- if (close(fh) == -1) {
- perror("close");
+ args.msr = idx;
+ if (ioctl(fh, CPU_RDMSR, &args) != 0) {
+ if (close(fh) == -1) {
+ perror("close");
exit(EXIT_FAILURE);
}
return 0;
}
- *val = args.data;
+ *val = args.data;
if (close(fh)==-1) {
perror("close");
@@ -116,25 +116,25 @@
#endif /* __FreeBSD__ */
-void dumpmsr (int cpu, unsigned int msr, int size)
+void dumpmsr(int cpu, unsigned int msr, int size)
{
unsigned long long val=0;
if (read_msr(cpu, msr, &val) == 1) {
if (size==32){
- printf ("MSR: 0x%08x=0x%08lx : ", msr, (unsigned long) val);
+ printf("MSR: 0x%08x=0x%08lx : ", msr, (unsigned long) val);
binary32(val);
}
if (size==64) {
- printf ("MSR: 0x%08x=0x%016llx : ", msr, val);
+ printf("MSR: 0x%08x=0x%016llx : ", msr, val);
binary64(val);
}
return;
}
- printf ("Couldn't read MSR 0x%x\n", msr);
+ printf("Couldn't read MSR 0x%x\n", msr);
}
-void dumpmsr_bin (int cpu, unsigned int msr, int size)
+void dumpmsr_bin(int cpu, unsigned int msr, int size)
{
unsigned long long val=0;
@@ -145,5 +145,5 @@
binary64(val);
return;
}
- printf ("Couldn't read MSR 0x%x\n", msr);
+ printf("Couldn't read MSR 0x%x\n", msr);
}
|
|
[-]
[+]
|
Added |
x86info-1.24.tar.bz2/results/Centaur
^
|
| +(directory)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Ezra-T.txt
^
|
| (renamed to results/Centaur/C3-Ezra-T.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Ezra-T.txt
^
|
| (renamed to results/Centaur/C3-Ezra-T.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Ezra.txt
^
|
| (renamed to results/Centaur/C3-Ezra.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Ezra.txt
^
|
| (renamed to results/Centaur/C3-Ezra.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Nehemiah-ES1.txt
^
|
| (renamed to results/Centaur/C3-Nehemiah-ES1.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Nehemiah-ES1.txt
^
|
| (renamed to results/Centaur/C3-Nehemiah-ES1.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Nehemiah-ES2.txt
^
|
| (renamed to results/Centaur/C3-Nehemiah-ES2.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C3-Nehemiah-ES2.txt
^
|
| (renamed to results/Centaur/C3-Nehemiah-ES2.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C7-Esther.txt
^
|
| (renamed to results/Centaur/C7-Esther.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/C7-Esther.txt
^
|
| (renamed to results/Centaur/C7-Esther.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/cyrix3-samuel.txt
^
|
| (renamed to results/Centaur/cyrix3-samuel.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/results/Centaur/cyrix3-samuel.txt
^
|
| (renamed to results/Centaur/cyrix3-samuel.txt)
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/x86info.c
^
|
| @@ -1,6 +1,5 @@
/*
- * This file is part of x86info.
- * (C) 2001-2007 Dave Jones.
+ * (C) 2001-2009 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*/
@@ -11,6 +10,9 @@
#include <unistd.h>
#include "x86info.h"
+#include "mptable.h"
+
+#include "Intel/Intel.h"
int show_bench=0;
int show_bios=0;
@@ -41,10 +43,10 @@
static void usage (char *programname)
{
- printf ("Usage: %s [<switches>]\n\
+ printf("Usage: %s [<switches>]\n\
-a, --all\n\
--bench\n\
- --bios\n\
+ --bios\n\
--bugs\n\
-c, --cache\n\
--connector\n\
@@ -89,8 +91,8 @@
need_root = 1;
}
-// if (!strcmp(arg, "--bench"))
-// show_bench = 1;
+ if (!strcmp(arg, "--bench"))
+ show_bench = 1;
if (!strcmp(arg, "--bios")) {
need_root = 1;
@@ -165,8 +167,8 @@
int j;
for (j=0; j<74; j++)
- printf ("-");
- printf ("\n");
+ printf("-");
+ printf("\n");
}
@@ -177,37 +179,37 @@
parse_command_line(argc, argv);
if (!silent) {
- printf ("x86info v1.21. Dave Jones 2001-2007\n");
- printf ("Feedback to <davej@redhat.com>.\n\n");
+ printf("x86info v1.24. Dave Jones 2001-2009\n");
+ printf("Feedback to <davej@redhat.com>.\n\n");
}
- if ((HaveCPUID())==0) {
- printf ("No CPUID instruction available.\n");
- printf ("No further information available for this CPU.\n");
+ if ((HaveCPUID()) == 0) {
+ printf("No CPUID instruction available.\n");
+ printf("No further information available for this CPU.\n");
return 0;
}
- if (getuid()!=0)
+ if (getuid() != 0)
user_is_root=0;
if (need_root && !user_is_root)
- printf ("Need to be root to use specified options.\n");
+ printf("Need to be root to use specified options.\n");
- nrCPUs = sysconf (_SC_NPROCESSORS_ONLN);
+ nrCPUs = sysconf(_SC_NPROCESSORS_ONLN);
if (!silent) {
- printf ("Found %u CPU", nrCPUs);
+ printf("Found %u CPU", nrCPUs);
if (nrCPUs > 1)
- printf ("s");
+ printf("s");
/* Check mptable if present. This way we get number of CPUs
on SMP systems that have booted UP kernels. */
if (user_is_root) {
nrSMPCPUs = enumerate_cpus();
if (nrSMPCPUs > nrCPUs)
- printf (", but found %ud CPUs in MPTable.", nrSMPCPUs);
+ printf(", but found %ud CPUs in MPTable.", nrSMPCPUs);
}
- printf ("\n");
+ printf("\n");
}
/*
@@ -229,11 +231,11 @@
for (i=0; i<nrCPUs; i++) {
cpu = malloc (sizeof (struct cpudata));
if (!cpu) {
- printf ("Out of memory\n");
+ printf("Out of memory\n");
return -1;
}
- memset (cpu, 0, sizeof(struct cpudata));
+ memset(cpu, 0, sizeof(struct cpudata));
if (!head) {
head = cpu;
@@ -244,20 +246,59 @@
cpu->number = i;
- if (!silent && nrCPUs!=1)
- printf ("CPU #%u\n", i+1);
+ if (!silent && nrCPUs != 1)
+ printf("CPU #%u\n", i+1);
+
+ bind_cpu(cpu);
estimate_MHz(cpu);
- identify (cpu);
- show_info (cpu);
+ get_feature_flags(cpu);
+ get_cpu_info_basics(cpu); /* get vendor,family,model,stepping */
+ identify(cpu);
+ show_info(cpu);
+
+ if (show_registers) {
+ dumpregs(cpu->number, 0, cpu->maxi);
+ if (cpu->maxei >=0x80000000)
+ dumpregs (cpu->number, 0x80000000, cpu->maxei);
+
+ if (cpu->maxei2 >=0xC0000000)
+ dumpregs (cpu->number, 0xC0000000, cpu->maxei2);
+ }
+
+ if (show_cacheinfo == 1) {
+ switch (cpu->vendor) {
+ case VENDOR_INTEL:
+ decode_Intel_caches(cpu, 1);
+ break;
+ case VENDOR_AMD:
+ decode_AMD_cacheinfo(cpu);
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (show_flags == 1)
+ show_feature_flags(cpu);
+
+ if (show_connector)
+ decode_connector(cpu->connector);
- /*
- * Doing this per-cpu is a problem, as we can't
- * schedule userspace code per-cpu.
- * Although running nrCPUs * threads would probably work.
- *
- * Could also experiment with the new scheduler binding syscalls.
- */
+ if (show_urls) {
+ if (cpu->datasheet_url != NULL)
+ printf("Datasheet: %s\n", cpu->datasheet_url);
+ if (cpu->errata_url != NULL)
+ printf("Errata: %s\n", cpu->errata_url);
+ }
+
+ /* Info that requires root access (eg, reading MSRs etc) */
+ if (user_is_root) {
+ if (show_mtrr)
+ dump_mtrrs(cpu);
+ }
+
+ /* Show MHz last. */
if (show_MHz) {
if (cpu->MHz < 1000)
printf("%uMHz", cpu->MHz);
@@ -268,12 +309,12 @@
printf("%u.%u%uGHz", a, b, (cpu->MHz - c)/10);
}
- printf (" processor (estimate).\n\n");
+ printf(" processor (estimate).\n\n");
}
if (show_bench)
- show_benchmarks();
+ show_benchmarks(cpu);
- if (nrCPUs>1)
+ if (nrCPUs > 1)
separator();
if (cpu->next)
@@ -292,9 +333,9 @@
cpu = tmp;
}
- if (nrCPUs > 1 && used_UP==1 && (!silent)) {
- printf ("WARNING: Detected SMP, but unable to access cpuid driver.\n");
- printf ("Used Uniprocessor CPU routines. Results inaccurate.\n");
+ if (nrCPUs > 1 && (used_UP == 1) && (!silent)) {
+ printf("WARNING: Detected SMP, but unable to access cpuid driver.\n");
+ printf("Used Uniprocessor CPU routines. Results inaccurate.\n");
}
return (0);
|
|
[-]
[+]
|
Changed |
x86info-1.24.tar.bz2/x86info.h
^
|
| @@ -1,18 +1,23 @@
#ifndef _X86INFO_H
#define _X86INFO_H
+#include "cpuid.h"
+
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
-#define VENDOR_AMD 1
-#define VENDOR_CENTAUR 2
-#define VENDOR_CYRIX 3
-#define VENDOR_INTEL 4
-#define VENDOR_NATSEMI 5
-#define VENDOR_RISE 6
-#define VENDOR_TRANSMETA 7
-#define VENDOR_SIS 8
+enum vendor {
+ VENDOR_UNKNOWN = 0 ,
+ VENDOR_AMD,
+ VENDOR_CENTAUR,
+ VENDOR_CYRIX,
+ VENDOR_INTEL,
+ VENDOR_NATSEMI,
+ VENDOR_RISE,
+ VENDOR_TRANSMETA,
+ VENDOR_SIS,
+};
enum connector {
CONN_UNKNOWN = 0,
@@ -48,6 +53,7 @@
CONN_SOCKET_F,
CONN_SOCKET_AM2,
CONN_SOCKET_S1G1,
+ CONN_SOCKET_S1G2,
CONN_SOCKET_F_R2,
CONN_SOCKET_AM2_R2,
};
@@ -56,14 +62,13 @@
struct cpudata {
struct cpudata *next;
unsigned int number;
- unsigned int vendor;
+ enum vendor vendor;
unsigned int efamily;
unsigned int family;
unsigned int model;
unsigned int emodel;
unsigned int stepping;
unsigned int type;
- unsigned int brand;
unsigned int cachesize_L1_I, cachesize_L1_D;
unsigned int cachesize_L2;
unsigned int cachesize_L3;
@@ -76,8 +81,14 @@
unsigned int eflags_ecx;
unsigned int eflags_edx;
unsigned int MHz;
- char * datasheet_url;
- char * errata_url;
+ unsigned int nr_cores;
+ unsigned int nr_logical;
+ char *datasheet_url;
+ char *errata_url;
+ /* Intel specific bits */
+ unsigned int brand;
+ unsigned int apicid;
+ char serialno[30];
};
#define family(c) (c->family + c->efamily)
@@ -98,28 +109,24 @@
return NULL; \
}
-extern void cpuid (int, unsigned int, unsigned long *, unsigned long *, unsigned long *, unsigned long *);
-extern void cpuid_UP (int, unsigned long *, unsigned long *, unsigned long *, unsigned long *);
-
extern void Identify_AMD (struct cpudata *cpu);
extern void Identify_Cyrix (struct cpudata *cpu);
-extern void Identify_IDT (struct cpudata *cpu);
+extern void identify_centaur(struct cpudata *cpu);
extern void Identify_Intel (struct cpudata *cpu);
-extern void Identify_RiSE (struct cpudata *cpu);
-extern void Identify_NatSemi (struct cpudata *cpu);
-extern void Identify_SiS (struct cpudata *cpu);
+extern void identify_RiSE(struct cpudata *cpu);
+extern void identify_natsemi(struct cpudata *cpu);
+extern void identify_sis(struct cpudata *cpu);
extern void display_AMD_info(struct cpudata *cpu);
extern void display_Cyrix_info(struct cpudata *cpu);
-extern void display_IDT_info(struct cpudata *cpu);
+extern void display_centaur_info(struct cpudata *cpu);
extern void display_Intel_info(struct cpudata *cpu);
-extern void display_NatSemi_info(struct cpudata *cpu);
-extern void display_RiSE_info(struct cpudata *cpu);
-extern void display_SiS_info(struct cpudata *cpu);
-
-extern void decode_feature_flags (struct cpudata *cpu);
-extern void identify (struct cpudata *cpu);
-extern void show_info (struct cpudata *cpu);
+
+extern void get_feature_flags(struct cpudata *cpu);
+extern void show_feature_flags(struct cpudata *cpu);
+extern void get_cpu_info_basics(struct cpudata *cpu);
+extern void identify(struct cpudata *cpu);
+extern void show_info(struct cpudata *cpu);
extern int read_msr(int cpu, unsigned int idx, unsigned long long *val);
extern void binary(unsigned int n, unsigned long value);
@@ -127,17 +134,22 @@
extern void binary64(unsigned long long value);
extern void dumpmsr (int cpunum, unsigned int msr, int size);
extern void dumpmsr_bin (int cpunum, unsigned int msr, int size);
+extern void dumpregs(int cpunum, unsigned int begin, unsigned int end);
extern void dump_mtrrs (struct cpudata *cpu);
extern void estimate_MHz(struct cpudata *cpu);
extern int HaveCPUID(void);
extern void interpret_eblcr(u32 lo);
-extern int issmp(int verb);
extern int enumerate_cpus(void);
-extern void get_model_name (struct cpudata *cpu);
+extern void get_model_name(struct cpudata *cpu);
extern void decode_connector(enum connector type);
-extern void show_benchmarks (void);
+extern void show_benchmarks(struct cpudata *cpu);
+extern void decode_serial_number(struct cpudata *cpu);
+
+extern void show_intel_topology(struct cpudata *cpu);
+
+void decode_AMD_cacheinfo(struct cpudata *cpu);
extern int show_bench;
extern int show_bios;
@@ -162,4 +174,20 @@
#define X86_FEATURE_MTRR 1<<12
+#define _GNU_SOURCE
+#define __USE_GNU
+#include <sched.h>
+#include <sys/types.h>
+#include <unistd.h>
+static inline void bind_cpu(struct cpudata *cpu)
+{
+ cpu_set_t set;
+
+ if (sched_getaffinity(getpid(), sizeof(set), &set) == 0) {
+ CPU_ZERO(&set);
+ CPU_SET(cpu->number, &set);
+ sched_setaffinity(getpid(), sizeof(set), &set);
+ }
+}
+
#endif /* _X86INFO_H */
|
