|
[-]
[+]
|
Added |
x86info.changes
|
|
|
|
[-]
[+]
|
Changed |
x86info.spec
^
|
|
|
|
[-]
[+]
|
Deleted |
x86info-1.24.tar.bz2/AMD/bluesmoke.c
^
|
| @@ -1,119 +0,0 @@
-/*
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * Dump machine check registers.
- */
-
-#include <stdio.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include "../x86info.h"
-#include "AMD.h"
-
-#define MCG_CAP 0x0179
-#define MCG_STATUS 0x17a
-#define MCG_CTL 0x17b
-
-#define MC_CTL 0x0400
-#define MC_STATUS 0x0401
-#define MC_ADDR 0x402
-#define MC_MISC 0x403
-
-void decode_athlon_bluesmoke(int cpunum)
-{
- unsigned long long val, val2;
- unsigned int banks, i;
-
- if (!user_is_root)
- return;
-
- if (read_msr(cpunum, MCG_CAP, &val) != 1)
- return;
-
- if ((val & (1<<8)) == 0)
- printf("Erk, MCG_CTL not present! :%016llx:\n", val);
-
- banks = val & 0xf;
-
- printf("Number of reporting banks : %d\n\n", banks);
-
- if (read_msr(cpunum, MCG_STATUS, &val) == 1) {
- if (val != 0) {
- printf(" 31 23 15 7 \n");
- printf("MCG_STATUS: ");
- dumpmsr_bin (cpunum, MCG_STATUS, 32);
- }
- }
-
- if (read_msr(cpunum, MCG_CTL, &val) == 1) {
- printf("MCG_CTL:\n");
-
- printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
- if ((val & (1<<0)) == 1) {
- if (read_msr(cpunum, MC_CTL, &val2) == 1) {
- printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
- }
- }
-
- printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
- if (((val & (1<<1)) == 2) && (banks>1)) {
- if (read_msr(cpunum, MC_CTL+4, &val2) == 1) {
- printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
- printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
- printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
- printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
- }
- }
-
- printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
- if ((val & (1<<2)) == 4 && (banks>2)) {
- if (read_msr(cpunum, MC_CTL+8, &val2) == 1) {
- printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
- }
- }
-
- printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
- if ((val & (1<<3)) == 8 && (banks>3)) {
- if (read_msr(cpunum, MC_CTL+12, &val2) == 1) {
- printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
- }
- }
- }
- printf("\n");
-
-
- printf(" 31 23 15 7 \n");
- for (i=0; i<banks; i++) {
- printf("Bank: %u (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
- printf("MC%uCTL: ", i);
- dumpmsr_bin (cpunum, MC_CTL+i*4, 32);
- printf("MC%uSTATUS: ", i);
- dumpmsr_bin (cpunum, MC_STATUS+i*4, 32);
- printf("MC%uADDR: ", i);
- dumpmsr_bin (cpunum, MC_ADDR+i*4, 32);
- printf("MC%uMISC: ", i);
- dumpmsr_bin (cpunum, MC_MISC+i*4, 32);
- printf("\n");
- }
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.24.tar.bz2/Intel/MSR-PM.c
^
|
| @@ -1,83 +0,0 @@
-/*
- * (C) 2002 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * Intel Pentium M specific MSR information
- * See 24547203.pdf for more details.
- */
-
-#include <stdio.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include "../x86info.h"
-#include "Intel.h"
-
-void dump_centrino_MSRs (struct cpudata *cpu)
-{
- unsigned long long val = 0;
- int tcc = 0;
-
- if (!user_is_root)
- return;
-
- printf("Pentium M MSRs:\n");
-
- if (read_msr (cpu->number, MSR_IA32_PERF_STATUS, &val) == 1) {
- /*
- Voltage and frequency values derived from 1300MHz
- Pentium M in an IBM ThinkPad X31. Constants for
- voltage function derived from voltage points documented
- in Pentium M datasheet (Intel document 25261201.pdf,
- table 5), and ACPI power management tables.
-
- This register is specifically documented as
- implementation-defined, so it may not apply to
- other Enhanced SpeedStep enabled CPUs, or even other
- Pentium Ms.
- */
- unsigned uv = (unsigned)val & 0xffff;
- int volt = (uv & 0xff) * 16 + 700;
- int mhz = 100 * (uv & 0xff00) >> 8UL;
- printf(" Current performance mode is 0x%04x: %dMHz, %d.%dV\n",
- uv, mhz, volt/1000, volt%1000);
- }
- if (read_msr (cpu->number, MSR_IA32_MISC_ENABLE, &val) == 1) {
- printf(" Enabled: ");
- if (val & (1<<3)) {
- printf("TCC ");
- tcc = 1;
- }
- if (val & (1<<7))
- printf("PerfMon ");
- if (val & (1<<10))
- printf("FERR# ");
- if (val & (1<<11))
- printf("noBTS ");
- if (val & (1<<12))
- printf("noPEBS ");
- if (val & (1<<16))
- printf("EnhancedSpeedStep ");
-
- printf("\n");
- }
- if (tcc && read_msr (cpu->number, MSR_PM_THERM2_CTL, &val) == 1) { /* THERM2_CTL */
- printf(" Thermal monitor %d\n", (val & (1<<16)) ? 2 : 1);
- }
- if (read_msr (cpu->number, MSR_IA32_THERM_CONTROL, &val) == 1) {
- if (val & (1<<4)) {
- printf(" Software-controlled clock: %f%% duty cycle\n",
- ((val >> 1) & 7) / 8.);
- } else
- printf(" Software-controlled clock disabled (full speed)\n");
- }
- if (read_msr (cpu->number, MSR_IA32_THERM_STATUS, &val) == 1) { /* THERM_STATUS */
- printf(" Thermal status: ");
- if (val & (1<<0))
- printf("TooHot ");
- if (val & (1<<1))
- printf("WasTooHot ");
- printf("\n");
- }
- printf("\n");
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.24.tar.bz2/Intel/bluesmoke.c
^
|
| @@ -1,118 +0,0 @@
-/*
- * (C) 2001 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- *
- * Dump machine check registers.
- */
-
-#include <stdio.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include "../x86info.h"
-#include "Intel.h"
-
-#define MCG_CAP 0x0179
-#define MCG_CTL_PBIT 8
-#define MCG_EXT_PBIT 9
-#define MCG_STATUS 0x17a
-#define MCG_CTL 0x17b
-#define MCG_EXT 0x180
-
-#define MC_CTL 0x0400
-#define MC_STATUS 0x0401
-#define MC_ADDR 0x402
-
-void decode_Intel_bluesmoke(int cpunum, int family)
-{
- unsigned long long val, val2;
- int banks, i, extcount = 0;
-
- if (!user_is_root)
- return;
-
- if (read_msr(cpunum, MCG_CAP, &val) != 1)
- return;
-
- banks = val & 0xff;
-
- printf("\nNumber of reporting banks : %d\n\n", banks);
-
- if (family == 0xf) {
- if ((val & (1<<MCG_EXT_PBIT))) {
- extcount = (val >> 16) & 0xff;
- printf("Number of extended MC registers : %d\n\n", extcount);
- }
- else
- printf("Erk, MCG_EXT not present! :%016llx:\n", val);
- }
- else
- if ((val & (1<<MCG_CTL_PBIT)) == 0)
- printf("Erk, MCG_CTL not present! :%016llx:\n", val);
-
- if (read_msr(cpunum, MCG_CTL, &val) == 1) {
- printf("MCG_CTL:\n");
-
- printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
- if ((val & (1<<0)) == 1) {
- if (read_msr(cpunum, MC_CTL, &val2) == 1) {
- printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
- }
- }
-
- printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
- if (((val & (1<<1)) == 2) && (banks>1)) {
- if (read_msr(cpunum, MC_CTL+4, &val2) == 1) {
- printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
- printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
- printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
- printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
- }
- }
-
- printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
- if ((val & (1<<2)) == 4 && (banks>2)) {
- if (read_msr(cpunum, MC_CTL+8, &val2) == 1) {
- printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
- printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
- printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
- printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
- printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
- printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
- }
- }
-
- printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
- if ((val & (1<<3)) == 8 && (banks>3)) {
- if (read_msr(cpunum, MC_CTL+12, &val2) == 1) {
- printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
- printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
- }
- }
- }
- printf("\n");
-
- for (i=0; i<banks; i++) {
- printf("Bank: %d (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
- printf("MC%dCTL: ", i);
- dumpmsr_bin (cpunum, MC_CTL+i*4, 64);
- printf("MC%dSTATUS: ", i);
- dumpmsr_bin (cpunum, MC_STATUS+i*4, 64);
- printf("MC%dADDR: ", i);
- dumpmsr_bin (cpunum, MC_ADDR+i*4, 64);
- printf("\n");
- }
-}
|
|
[-]
[+]
|
Deleted |
x86info-1.24.tar.bz2/cpuid.h
^
|
| @@ -1,11 +0,0 @@
-#ifndef _CPUID_H
-#define _CPUID_H
-
-extern void cpuid_UP (unsigned int idx, unsigned long *eax, unsigned long *ebx,
- unsigned long *ecx, unsigned long *edx);
-extern void cpuid(unsigned int cpu, unsigned long long idx, unsigned int *eax,
- unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
-extern void cpuid4(unsigned int cpu, unsigned long long idx, unsigned int *eax,
- unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
-
-#endif /* _CPUID_H */
|
|
[-]
[+]
|
Deleted |
x86info-1.24.tar.bz2/dumpregs.c
^
|
| @@ -1,21 +0,0 @@
-/*
- * (C) 2001,2008 Dave Jones.
- *
- * Licensed under the terms of the GNU GPL License version 2.
- */
-
-#include <stdio.h>
-#include "x86info.h"
-
-void dumpregs(int cpunum, unsigned int begin, unsigned int end)
-{
- unsigned int i;
- unsigned int eax, ebx, ecx, edx;
-
- /* Dump all the CPUID results in raw hex */
- for (i=begin; i<=end; i++) {
- cpuid(cpunum, i, &eax, &ebx, &ecx, &edx);
- printf("eax in: 0x%08x, eax = %08x ebx = %08x ecx = %08x edx = %08x\n", i, eax, ebx, ecx, edx);
- }
- printf("\n");
-}
|
|
|
Deleted |
x86info-1.25.tar.bz2
^
|
|
|
Deleted |
x86info-1.27.tar.bz2
^
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/.gitignore
^
|
| @@ -2,6 +2,8 @@
*.P
x86info
AMD/fam10h.h
+AMD/fam11h.h
AMD/k8.h
generic_msr.h
lsmsr
+x86info-1.*.tgz
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/AMD.h
^
|
| @@ -8,7 +8,7 @@
#ifndef _AMD_H
#define _AMD_H
-extern void decode_athlon_bluesmoke(int cpunum);
+extern void decode_athlon_machine_check(int cpunum);
extern void dump_athlon_MSR(struct cpudata *cpu);
extern void dump_k6_MSR (struct cpudata *cpu);
extern void decode_powernow (struct cpudata *cpu);
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/dumppsb.c
^
|
| @@ -88,8 +88,6 @@
p += sizeof (struct psb_s);
- pst = (struct pst_s *) p;
-
for (i=0 ; i<psb->numpst; i++) {
pst = (struct pst_s *) p;
numpstates = pst->numpstates;
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/fam10h.regs
^
|
| @@ -1,9 +1,9 @@
# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
#
-# Copyright (C) 2008 Advanced Micro Devices, Inc.
+# Copyright (C) 2008, 2009 Advanced Micro Devices, Inc.
# This file contains information from:
-# - "31116 Rev 3.06 - March 2008, BIOS and Kernel Developer's Guide (BKDG)
+# - "31116 Rev 3.48 - April 2010, BIOS and Kernel Developer's Guide (BKDG)
# for AMD Family 10h Processors"
# See scripts/createheader.py for the general format of this register
@@ -14,6 +14,7 @@
:16
} # alias of MC3_ADDR
+# to be updated 24-31 bits 8:15 of syndrome
{LSMCAstatus=0x0001;load-store MCE status
ErrorCode:16
ErrorCodeExt:4
@@ -50,6 +51,11 @@
:46
}
+{PATCH_LEVEL=0x008b;microcode patch level
+ PATCH_LEVEL:32
+ :32
+}
+
{MTRRcap=0x00fe;MTRR capabilities
MtrrCapVCnt:8
MtrrCapFix:1
@@ -572,10 +578,7 @@
ErrorCodeExt:5
:3
Syndrome:8
- ErrCpu0:1
- ErrCpu1:1
- ErrCpu2:1
- ErrCpu3:1
+ ErrCpu:4
LDTLink0:1
LDTLink1:1
LDTLink2:1
@@ -1111,7 +1114,8 @@
IntrPndMsg:1
IORd:1
SmiOnCmpHalt:1
- :36
+ C1eOnCmpHalt:1
+ :35
}
{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle
@@ -1310,7 +1314,7 @@
VM_HSAVE_PA:64
}
-# {SMM_CTL=0xc0010118;SVM lock key
+# {SVMLock=0xc0010118;SVM lock key
# SvmLockKey:64
# } # write-only
@@ -1341,17 +1345,38 @@
}
{CPUIDFeatures=0xc0011004;CPUID features
- Features:32
- Features:32
+ FeaturesEdx:32
+ FeaturesEcx:32
}
{CPUIDExtFeatures=0xc0011005;extended CPUID features
- ExtFeaturesEcx:32
ExtFeaturesEdx:32
+ ExtFeaturesEcx:32
+}
+
+{NodeId=0xc001100c;Node ID
+ NodeId:3
+ NodesPerProcessor:3
+ BiosScratch:6
+ :52
+}
+
+{IC_CFG=0xc0011021;instruction cache configuration
+ :9
+ DIS_SPEC_TLB_RLD:1
+ :4
+ DIS_IND:1
+ :39
}
{DC_CFG=0xc0011022;data cache configuration
- :34
+ :4
+ DIS_SPEC_TLB_RLD:1
+ :3
+ DIS_CLR_WBTOL2_SMC_HIT:1
+ :4
+ DIS_HW_PF:1
+ :20
REQ_CTR:2
:28
}
@@ -1365,11 +1390,19 @@
{BU_CFG2=0xc001102A;bus unit configuration 2
:2
FrcWTMemTypToWPDis:1
- :12
+ :3
+ ThrottleNbInterface:2
+ :7
CILinesToNbDis:1
:13
Smash1GPages:1
- :34
+ :6
+ ThrottleNbInterface:2
+ :4
+ ProbeFilterSupEn:1
+ :7
+ RdMmExtCfgQwEn:1
+ :13
}
{IbsFetchCtl=0xc0011030;IBS fetch control
@@ -1401,7 +1434,10 @@
:1
IbsOpEn:1
IbsOpVal:1
- :45
+ IbsOpCntCtl:1
+ :12
+ IbsOpCurCnt:20
+ :12
}
{IbsOpRip=0xc0011034;IBS Op logical address
@@ -1448,7 +1484,8 @@
IbsDcMabHit:1
IbsDcLinAddrValid:1
IbsDcPhyAddrValid:1
- :13
+ IbsDcL2tlbHit1G:1
+ :12
IbsDcMissLat:16
:16
}
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/AMD/fam11h.regs
^
|
| @@ -0,0 +1,1246 @@
+# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+#
+# Copyright (C) 2009 Advanced Micro Devices, Inc.
+
+# This source file contains information based on:
+# - "41526 Rev 3.00 - July 07, 2008, AMD Family 11h Processor BKDG"
+
+# See scripts/createheader.py for the general format of this register
+# definitions.
+
+{LSMCAaddr=0x0000;load-store MCA address
+ ADDR:48
+ :16
+} # alias of MC3_ADDR
+
+{LSMCAstatus=0x0001;load-store MCA status
+ ErrorCode:16
+ :29
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+} # alias of MC3_STATUS
+
+{TSC=0x0010;time-stamp counter
+ TSC:64
+}
+
+{APIC_BASE=0x001b;APIC base address
+ :8
+ BSC:1
+ :2
+ ApicEn:1
+ ApicBar:36
+ :16
+}
+
+{EBL_CR_POWERON=0x002a;cluster ID
+ :16
+ ClusterID:2
+ :46
+}
+
+{PATCH_LEVEL=0x008b;microcode patch level
+ PATCH_LEVEL:32
+ :32
+}
+
+{MTRRcap=0x00fe;MTRR capabilities
+ MtrrCapVCnt:8
+ MtrrCapFix:1
+ :1
+ MtrrCapWc:1
+ :53
+}
+
+{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector
+ SYSENTER_CS:16
+ :48
+}
+
+{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer
+ SYSENTER_ESP:32
+ :32
+}
+
+{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer
+ SYSENTER_EIP:32
+ :32
+}
+
+{MCG_CAP=0x0179;global MC capabilities
+ Count:8
+ MCG_CTL_P:1
+ :55
+}
+
+{MCG_STAT=0x017a;global MC status
+ RIPV:1
+ EIPV:1
+ MCIP:1
+ :61
+}
+
+{MCG_CTL=0x017b;global MC control
+ DCE:1
+ ICE:1
+ BUE:1
+ LSE:1
+ NBE:1
+ FRE:1
+ :58
+}
+
+{DBG_CTL_MSR=0x01d9;debug control
+ LBR:1
+ BTF:1
+ PB0:1
+ PB1:1
+ PB2:1
+ PB3:1
+ :58
+}
+
+{BR_FROM=0x01db;last branch from IP
+ LastBranchFromIP:64
+}
+
+{BR_TO=0x01dc;last branch to IP
+ LastBranchToIP:64
+}
+
+{LastExceptionFromIP=0x01dd;last exception from IP
+ LastIntFromIP:64
+}
+
+{LastExceptionToIP=0x01de;last exception to IP
+ LastIntToIP:64
+}
+
+{MTRRphysBase0=0x0200;base of variable-size MTRR (0)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask0=0x0201;mask of variable-size MTRR (0)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase1=0x0202;base of variable-size MTRR (1)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask1=0x0203;mask of variable-size MTRR (1)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase2=0x0204;base of variable-size MTRR (2)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask2=0x0205;mask of variable-size MTRR (2)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase3=0x0206;base of variable-size MTRR (3)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask3=0x0207;mask of variable-size MTRR (3)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase4=0x0208;base of variable-size MTRR (4)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask4=0x0209;mask of variable-size MTRR (4)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase5=0x020a;base of variable-size MTRR (5)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask5=0x020b;mask of variable-size MTRR (5)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase6=0x020c;base of variable-size MTRR (6)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask6=0x020d;mask of variable-size MTRR (6)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRphysBase7=0x020e;base of variable-size MTRR (7)
+ MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
+ :4
+ PhyBase:36
+ :16
+}
+
+{MTRRphysMask7=0x020f;mask of variable-size MTRR (7)
+ :11
+ Valid:1
+ PhysMask:36
+ :16
+}
+
+{MTRRfix64K_00000=0x0250;fixed range MTRR
+ 0xxxxType:8
+ 1xxxxType:8
+ 2xxxxType:8
+ 3xxxxType:8
+ 4xxxxType:8
+ 5xxxxType:8
+ 6xxxxType:8
+ 7xxxxType:8
+}
+
+{MTRRfix16K_80000=0x0258;fixed range MTRR
+ 80xxxType:8
+ 84xxxType:8
+ 88xxxType:8
+ 8CxxxType:8
+ 90xxxType:8
+ 94xxxType:8
+ 98xxxType:8
+ 9CxxxType:8
+}
+
+{MTRRfix16K_A0000=0x0259;fixed range MTRR
+ A0xxxType:8
+ A4xxxType:8
+ A8xxxType:8
+ ACxxxType:8
+ B0xxxType:8
+ B4xxxType:8
+ B8xxxType:8
+ BCxxxType:8
+}
+
+{MTRRfix4K_C0000=0x0268;fixed range MTRR
+ C0xxxType:8
+ C1xxxType:8
+ C2xxxType:8
+ C3xxxType:8
+ C4xxxType:8
+ C5xxxType:8
+ C6xxxType:8
+ C7xxxType:8
+}
+
+{MTRRfix4K_C8000=0x0269;fixed range MTRR
+ C8xxxType:8
+ C9xxxType:8
+ CAxxxType:8
+ CBxxxType:8
+ CCxxxType:8
+ CDxxxType:8
+ CExxxType:8
+ CFxxxType:8
+}
+
+{MTRRfix4K_D0000=0x026a;fixed range MTRR
+ D0xxxType:8
+ D1xxxType:8
+ D2xxxType:8
+ D3xxxType:8
+ D4xxxType:8
+ D5xxxType:8
+ D6xxxType:8
+ D7xxxType:8
+}
+
+{MTRRfix4K_D8000=0x026b;fixed range MTRR
+ D8xxxType:8
+ D9xxxType:8
+ DAxxxType:8
+ DBxxxType:8
+ DCxxxType:8
+ DDxxxType:8
+ DExxxType:8
+ DFxxxType:8
+}
+
+{MTRRfix4K_E0000=0x026c;fixed range MTRR
+ E0xxxType:8
+ E1xxxType:8
+ E2xxxType:8
+ E3xxxType:8
+ E4xxxType:8
+ E5xxxType:8
+ E6xxxType:8
+ E7xxxType:8
+}
+
+{MTRRfix4K_E8000=0x026d;fixed range MTRR
+ E8xxxType:8
+ E9xxxType:8
+ EAxxxType:8
+ EBxxxType:8
+ ECxxxType:8
+ EDxxxType:8
+ EExxxType:8
+ EFxxxType:8
+}
+
+{MTRRfix4K_F0000=0x026e;fixed range MTRR
+ F0xxxType:8
+ F1xxxType:8
+ F2xxxType:8
+ F3xxxType:8
+ F4xxxType:8
+ F5xxxType:8
+ F6xxxType:8
+ F7xxxType:8
+}
+
+{MTRRfix4K_F8000=0x026f;fixed range MTRR
+ F8xxxType:8
+ F9xxxType:8
+ FAxxxType:8
+ FBxxxType:8
+ FCxxxType:8
+ FDxxxType:8
+ FExxxType:8
+ FFxxxType:8
+}
+
+{PAT=0x0277;page attribute table
+ PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+ PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
+ :5
+}
+
+{MTRRdefType=0x02ff;MTRR default memory type
+ MemType:8
+ :2
+ MtrrDefTypeFixEn:1
+ MtrrDefTypeEn:1
+ :52
+}
+
+{MC0_CTL=0x0400;data cache MC control
+ ECCI:1
+ ECCM:1
+ DECC:1
+ DMTP:1
+ DSTP:1
+ L1TP:1
+ L2TP:1
+ :57
+}
+
+{MC0_STATUS=0x0401;data cache MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :20
+ Scrub:1
+ :4
+ UECC:1
+ CECC:1
+ Syndrome:8
+ :2
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC0_ADDR=0x0402;data cache MC address
+ ADDR:48
+ :16
+}
+
+{MC0_MISC=0x0403;data cache MC miscellaneous
+ :64
+}
+
+{MC1_CTL=0x0404;instruction cache MC control
+ ECCI:1
+ ECCM:1
+ IDP:1
+ IMTP:1
+ ISTP:1
+ L1TP:1
+ L2TP:1
+ :2
+ RDDE:1
+ :54
+}
+
+{MC1_STATUS=0x0405;instruction cache MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :25
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC1_ADDR=0x0406;instruction cache MC address
+ ADDR:48
+ :16
+}
+
+{MC1_MISC=0x0407;instruction cache MC miscellaneous
+ :64
+}
+
+{MC2_CTL=0x0408;bus unit MC control
+ S_RDE_HP:1
+ S_RDE_TLB:1
+ S_RDE_ALL:1
+ S_ECC1_TLB:1
+ S_ECC1_HP:1
+ S_ECCM_TLB:1
+ S_ECCM_HP:1
+ L2T_PAR_ICDC:1
+ L2T_PAR_TLB:1
+ L2_PAR_SNP:1
+ L2_PAR_CPB:1
+ L2_PAR_SCR:1
+ L2D_ECC1_TLB:1
+ L2D_ECC1_SNP:1
+ L2D_ECC1_CPB:1
+ L2D_ECCM_TLB:1
+ L2D_ECCM_SNP:1
+ L2D_ECCM_CPB:1
+ L2T_ECC1_SCR:1
+ L2T_ECCM_SCR:1
+ :44
+}
+
+{MC2_STATUS=0x0409;bus unit MC status
+ ErrorCode:16
+ ErrorCodeExt:4
+ :25
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ AddrV:1
+ MiscV:1
+ En:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC2_ADDR=0x040a;bus unit MC address register
+ ADDR:48
+ :16
+}
+
+{MC2_MISC=0x040b;bus unit MC miscellaneous
+ :64
+}
+
+{MC3_CTL=0x040c;load store unit MC control
+ S_RDE_L:1
+ S_RDE_S:1
+ :62
+}
+
+{MC3_STATUS=0x040d;load store unit MC status
+ ErrorCode:16
+ :29
+ UECC:1
+ CECC:1
+ :10
+ PCC:1
+ ADDRV:1
+ MISCV:1
+ EN:1
+ UC:1
+ OVER:1
+ VAL:1
+}
+
+{MC3_ADDR=0x040e;load store unit MC address
+ ADDR:48
+ :16
+}
+
+{MC3_MISC=0x040f;load store unit MC miscellaneous
+ :64
+}
+
+{MC4_CTL=0x0410;northbridge MC control
+ :2
+ CrcErr0En:1
+ :2
+ SyncPkt0En:1
+ :2
+ MstrAbrtEn:1
+ TgtAbrtEn:1
+ :1
+ AtomicRMWEn:1
+ WDTRptEn:1
+ DevErrEn:1
+ :2
+ HtProtEn:1
+ HtDataEn:1
+ :1
+ RtryHt0En:1
+ :5
+ McaUsPwDatErrEn:1
+ :1
+ TblWlkDatErrEn:1
+ :36
+}
+
+{MC4_STATUS=0x0411;northbridge MC status
+ ErrorCode:16
+ ErrorCodeExt:5
+ :11
+ ErrCpu0:1
+ ErrCpu1:1
+ :2
+ LDTLink:1
+ :4
+ SubLink:1
+ :15
+ PCC:1
+ AddrV:1
+ :1
+ En:1
+ UC:1
+ Over:1
+ Val:1
+}
+
+{MC4_ADDR=0x0412;northbridge MC address
+ NBaddr:64
+}
+
+# 0x0413 reserved (was MC4_MISC0)
+
+{EFER=0xc0000080;extended feature enable
+ SYSCALL:1
+ :7
+ LME:1
+ :1
+ LMA:1
+ NXE:1
+ SVME:1
+ LMSLE:1
+ FFXSE:1
+ :49
+}
+
+{STAR=0xc0000081;SYSCALL target address
+ Target:32
+ SysCallSel:16
+ SysRetSel:16
+}
+
+{STAR64=0xc0000082;long mode SYSCALL target address
+ LSTAR:64
+}
+
+{STARCOMPAT=0xc0000083;compat mode SYSCALL target address
+ CSTAR:64
+}
+
+{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask
+ MASK:32
+ :32
+}
+
+{FS_BASE=0xc0000100;FS base
+ FS_BASE:64
+}
+
+{GS_BASE=0xc0000101;GS base
+ GS_BASE:64
+}
+
+{KernelGSbase=0xc0000102;kernel GS base
+ KernelGSBase:64
+}
+
+{TSC_AUX=0xc0000103;auxiliary time stamp counter data
+ TscAux:32
+ :32
+}
+
+{PERF_CTL0=0xc0010000;performance event select (0)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ PC:1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :28
+}
+
+{PERF_CTL1=0xc0010001;performance event select (1)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ PC:1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :28
+}
+
+{PERF_CTL2=0xc0010002;performance event select (2)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ PC:1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :28
+}
+
+{PERF_CTL3=0xc0010003;performance event select (3)
+ EventSelect:8
+ UnitMask:8
+ User:1
+ OS:1
+ Edge:1
+ :1
+ Int:1
+ :1
+ En:1
+ Inv:1
+ CntMask:8
+ EventSelect:4
+ :28
+}
+
+{PERF_CTR0=0xc0010004;performance event counter (0)
+ CTR:48
+ :16
+}
+
+{PERF_CTR1=0xc0010005;performance event counter (1)
+ CTR:48
+ :16
+}
+
+{PERF_CTR2=0xc0010006;performance event counter (2)
+ CTR:48
+ :16
+}
+
+{PERF_CTR3=0xc0010007;performance event counter (3)
+ CTR:48
+ :16
+}
+
+{SYS_CFG=0xc0010010;system configuration
+ SysAckLimit:5
+ SysVicLimit:3
+ :1
+ SetDirtyEnS:1
+ SetDirtyEnO:1
+ :5
+ ChxToDirtyDis:1
+ SysUcLockEn:1
+ MtrrFixDramEn:1
+ MtrrFixDramModeEn:1
+ MtrrVarDramEn:1
+ MtrrTom2En:1
+ Tom2ForceMemTypeWB:1
+ :41
+}
+
+{HWCR=0xc0010015;hardware configuration
+ SmmLock:1
+ SlowFence:1
+ :1
+ TlbCacheDis:1
+ INVD_WBINVD:1
+ :1
+ FFDIS:1
+ DisLock:1
+ IgnneEm:1
+ :4
+ SmiSpCycDis:1
+ RsmSpCycDis:1
+ SseDis:1
+ :1
+ Wrap32Dis:1
+ McStatusWrEn:1
+ :1
+ IoCfgGpFault:1
+ :2
+ ForceUsRdWrSzPrb:1
+ TscFreqSel:1
+ :39
+}
+
+{IORR_BASE0=0xc0010016;base of variable I/O range (0)
+ :3
+ WrMem:1
+ RdMem:1
+ :7
+ PhyBase:36
+ :16
+}
+
+{IORR_MASK0=0xc0010017;mask of variable I/O range (0)
+ :11
+ Valid:1
+ PhyMask:36
+ :16
+}
+
+{IORR_BASE1=0xc0010018;base of variable I/O range (1)
+ :3
+ WrMem:1
+ RdMem:1
+ :7
+ PhyBase:36
+ :16
+}
+
+{IORR_MASK1=0xc0010019;mask of variable I/O range (1)
+ :11
+ Valid:1
+ PhyMask:36
+ :16
+}
+
+{TOP_MEM=0xc001001a;top of memory address
+ :23
+ TOM:17
+ :24
+}
+
+{TOM2=0xc001001d;second top of memory address
+ :23
+ TOM2:17
+ :24
+}
+
+{NB_CFG=0xc001001f;northbridge configuration
+ :42
+ EnaPStateSpyCyc:1
+ :2
+ DisUsSysMgtReqToNcHt:1
+ EnableCf8ExtCfg:1
+ :3
+ DisOrderRdRsp:1
+ :7
+ EnConvertToNonIsoc:1
+ :5
+}
+
+{ProcessorNameString0=0xc0010030;processor name string (0)
+ CpuNameString:64
+}
+
+{ProcessorNameString1=0xc0010031;processor name string (1)
+ CpuNameString:64
+}
+
+{ProcessorNameString2=0xc0010032;processor name string (2)
+ CpuNameString:64
+}
+
+{ProcessorNameString3=0xc0010033;processor name string (3)
+ CpuNameString:64
+}
+
+{ProcessorNameString4=0xc0010034;processor name string (4)
+ CpuNameString:64
+}
+
+{ProcessorNameString5=0xc0010035;processor name string (5)
+ CpuNameString:64
+}
+
+{MC0_CTL_MASK=0xc0010044;data cache MC control mask
+ ECCI:1
+ ECCM:1
+ DECC:1
+ DMTP:1
+ DSTP:1
+ L1TP:1
+ L2TP:1
+ :57
+}
+
+{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask
+ ECCI:1
+ ECCM:1
+ IDP:1
+ IMTP:1
+ ISTP:1
+ L1TP:1
+ L2TP:1
+ :2
+ RDDE:1
+ :54
+}
+
+{MC2_CTL_MASK=0xc0010046;bus unit MC control mask
+ S_RDE_HP:1
+ S_RDE_TLB:1
+ S_RDE_ALL:1
+ S_ECC1_TLB:1
+ S_ECC1_HP:1
+ S_ECCM_TLB:1
+ S_ECCM_HP:1
+ L2T_PAR_ICDC:1
+ L2T_PAR_TLB:1
+ L2_PAR_SNP:1
+ L2_PAR_CPB:1
+ L2_PAR_SCR:1
+ L2D_ECC1_TLB:1
+ L2D_ECC1_SNP:1
+ L2D_ECC1_CPB:1
+ L2D_ECCM_TLB:1
+ L2D_ECCM_SNP:1
+ L2D_ECCM_CPB:1
+ L2T_ECC1_SCR:1
+ L2T_ECCM_SCR:1
+ :44
+}
+
+{MC3_CTL_MASK=0xc0010047;load store unit MC control mask
+ S_RDE_L:1
+ S_RDE_S:1
+ :62
+}
+
+{MC4_CTL_MASK=0xc0010048;northbridge MC control mask
+ :2
+ CrcErr0En:1
+ :2
+ SyncPkt0En:1
+ :2
+ MstrAbrtEn:1
+ TgtAbrtEn:1
+ :1
+ AtomicRMWEn:1
+ WDTRptEn:1
+ DevErrEn:1
+ :2
+ HtProtEn:1
+ HtDataEn:1
+ :1
+ RtryHt0En:1
+ :5
+ McaUsPwDatErrEn:1
+ :1
+ TblWlkDatErrEn:1
+ :36
+}
+
+{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3)
+ SmiAddr:32
+ SmiMask:24
+ :5
+ ConfigSmi:1
+ SmiOnWrEn:1
+ SmiOnRdEn:1
+}
+
+{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control
+ :1
+ SmiEn_0:1
+ :1
+ SmiEn_1:1
+ :1
+ SmiEn_2:1
+ :1
+ SmiEn_3:1
+ :7
+ IoTrapEn:1
+ :48
+}
+
+{IntPendingMessage=0xc0010055;interrupt pending and CMP-halt
+ IOMsgAddr:16
+ IOMsgData:8
+ IntrPndMsgDis:1
+ IntrPndMsg:1
+ IORd:1
+ SmiOnCmpHalt:1
+ C1eOnCmpHalt:1
+ :35
+}
+
+{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle
+ IoPortAddress:16
+ IoData:8
+ :1
+ IoCycleEn:1
+ IoRd:1
+ :37
+}
+
+{MmioConfigBase=0xc0010058;MMIO configuration base address
+ Enable:1
+ :1
+ BusRange:4;0=1;1=2;2;4;3=8;4=16;5=32;6=64;7=128;8=256
+ :14
+ MmiocCfgBaseAddr:20
+ :24
+}
+
+{BISTresults=0xc0010060;BIST results register
+ ICFT:1
+ ICST:1
+ ICTLB2:1
+ BTA:1
+ BSA:1
+ ICD:1
+ PDA:1
+ BH:1
+ ICTLB1:1
+ ICLRU:1
+ BSR:1
+ DCD:1
+ DCECC:1
+ DCTLB1:1
+ DCT:1
+ DCTLB2:1
+ DCLRU:1
+ FPCR:1
+ FPRR:1
+ FPRQ:1
+ :2
+ ROBD:1
+ L2D:1
+ L2T:1
+ WDB:1
+ VDB:1
+ L2LRU:1
+ FF:1
+ PDC:1
+ :1
+ MC:1
+ :32
+}
+
+{PstateCurrentLimit=0xc0010061;P-state current limit
+ CurPstateLimit:3
+ :1
+ PstateMaxVal:3
+ :57
+}
+
+{PstateControl=0xc0010062;P-state control
+ PstateCmd:3
+ :61
+}
+
+{PstateStatus=0xc0010063;P-state status
+ CurPstate:3
+ :61
+}
+
+{Pstate0=0xc0010064;P-state 0
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate1=0xc0010065;P-state 1
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate2=0xc0010066;P-state 2
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate3=0xc0010067;P-state 3
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate4=0xc0010068;P-state 4
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate5=0xc0010069;P-state 5
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate6=0xc001006a;P-state 6
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{Pstate7=0xc001006b;P-state 7
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ :16
+ IddValue:8
+ IddDiv:2
+ :21
+ PstateEn:1
+}
+
+{COFVIDcontrol=0xc0010070;COFVID control
+ CpuFid:6
+ CpuDid:3
+ CpuVid:7
+ PstateId:3
+ :45
+}
+
+{COFVIDstatus=0xc0010071;COFVID status
+ CurCpuFid:6
+ CurCpuDid:3
+ CurCpuVid:7
+ CurPstate:3
+ :6
+ CurNbVid:7
+ StartupPstate:3
+ MaxVid:7
+ MinVid:7
+ MainPllOpFreqIdMax:6
+ :1
+ CurPstateLimit:3
+ :5
+}
+
+{SMM_BASE=0xc0010111;SMM base address
+ SMM_BASE:32
+ :32
+}
+
+{SMMAddr=0xc0010112;SMM TSeg base address
+ :17
+ TSegBase:23
+ :24
+}
+
+{SMMMask=0xc0010113;SMM Tseg mask
+ AValid:1
+ TValid:1
+ AClose:1
+ TClose:1
+ AMTypeIoWc:1
+ TMTypeIoWc:1
+ :2
+ AMTypeDram:3
+ :1
+ TMTypeDram:3
+ :2
+ TSegMask:23
+ :24
+}
+
+{VM_CR=0xc0010114;virtual machine control
+ dpd:1
+ r_init:1
+ dis_a20m:1
+ Lock:1
+ Svme_Disable:1
+ :59
+}
+
+{IGNNE=0xc0010115;IGNNE
+ IGNNE:1
+ :63
+}
+
+# 0xc0010116 SMM_CTL, write-only
+
+{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address
+ VM_HSAVE_PA:64
+}
+
+# 0xc0010118 SVM Lock key, write-only
+
+{OSVW_ID_Length=0xc0010140;OS visible work-around ID length
+ OSVW_ID_Length:16
+ :48
+}
+
+{OsvwStatus=0xc0010141;OS visible work-around status
+ OsvwStatusBits:64
+}
+
+{DC_CFG=0xc0011022;data cache configuration register
+ :8
+ DIS_CLR_WBTOL2_SMC_HIT:1
+ :4
+ DIS_HW_PF:1
+ :1
+ DIS_PF_HW_FOR_SW:1
+ :48
+}
+
+{BU_CFG=0xc0011023;bus unit configuration register
+ :48
+ WbEnhWsbDis:1
+ :15
+}
+
+### Local Variables: ###
+### mode:shell-script ###
+### End: ###
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/identify.c
^
|
| @@ -18,20 +18,17 @@
#include "revision.h"
static char *amd_nameptr;
-#define add_to_cpuname(x) \
-do { \
- amd_nameptr += snprintf(amd_nameptr, sizeof(x), "%s", x); \
-} while(0)
+#define add_to_cpuname(x) amd_nameptr += snprintf(amd_nameptr, sizeof(x), "%s", x)
static void set_k8_name(struct k8_rev *r, struct cpudata *c)
{
- int i, id, cont;
+ unsigned int i, id, cont;
char s[CPU_NAME_LEN];
const char *p;
s[0] = 0;
cont = 0;
- for (i=0; (r != NULL) && (i<ARRAY_SIZE(k8_names)); i++) {
+ for (i = 0; (r != NULL) && (i < ARRAY_SIZE(k8_names)); i++) {
p = NULL;
id = 1<<i;
if (r->nameid & id)
@@ -57,7 +54,7 @@
c->connector = 0;
r = NULL;
- for (i=0; i<ARRAY_SIZE(k8_revisions); i++) {
+ for (i = 0; i < ARRAY_SIZE(k8_revisions); i++) {
if (k8_revisions[i].eax == id) {
r = &k8_revisions[i];
break;
@@ -76,13 +73,9 @@
return;
}
- if (r->nameid & _PHENOM)
- snprintf(c->name, CPU_NAME_LEN,
- "Quad-Core Opteron/Phenom (%s)",
- r->rev);
- else if (r->nameid)
- snprintf(c->name, CPU_NAME_LEN,
- "Quad-Core Opteron (%s)", r->rev);
+ snprintf(c->name, CPU_NAME_LEN,
+ "Phenom/Athlon/Sempron/Turion (II)/Opteron (%s)",
+ r->rev);
}
static void set_connector(struct cpudata *c)
@@ -90,6 +83,11 @@
unsigned int eax, ebx, ecx, edx;
int pkg_id;
+ if (family(c) == 0x11) {
+ c->connector = CONN_SOCKET_S1G2;
+ return;
+ }
+
cpuid(c->number, 0x80000001, &eax, &ebx, &ecx, &edx);
pkg_id = (ebx >> 28) & 0xf;
@@ -98,11 +96,19 @@
c->connector = CONN_SOCKET_F_R2;
break;
case 1:
- c->connector = CONN_SOCKET_AM2_R2;
+ c->connector = CONN_SOCKET_AM3;
break;
case 2:
- c->connector = CONN_SOCKET_S1G2;
+ c->connector = CONN_SOCKET_S1G3;
+ break;
+ case 3:
+ c->connector = CONN_SOCKET_G34;
+ break;
+ case 4:
+ c->connector = CONN_SOCKET_ASB2;
break;
+ case 5:
+ c->connector = CONN_SOCKET_C32;
default:
c->connector = 0;
}
@@ -113,7 +119,7 @@
int i;
struct fam10h_rev *r = NULL;
- for (i=0; i<ARRAY_SIZE(fam10h_revisions); i++) {
+ for (i = 0; i < ARRAY_SIZE(fam10h_revisions); i++) {
if (fam10h_revisions[i].eax == id) {
r = &fam10h_revisions[i];
break;
@@ -128,7 +134,7 @@
const char *p;
p = get_fam11h_revision_name(id);
- if(p)
+ if (p)
snprintf(c->name, CPU_NAME_LEN,
"AMD Turion X2 Ultra Dual-Core (%s)", p);
else
@@ -289,14 +295,18 @@
printf("lines per tag=%u\t", (ecx >> 8) & 0x0f);
printf("line size=%u bytes.\n", ecx & 0xff);
if (family(cpu) == 0x10) {
- /* family 0x10 has shared L3 cache */
printf("L3 (shared) cache:\n\t");
- printf("Size: %uKb\t",
- (edx >> 18) * 512);
- do_l2assoc((edx >> 12) & 0x0f);
- printf("\n\t");
- printf("lines per tag=%u\t", (edx >> 8) & 0x0f);
- printf("line size=%u bytes.\n", edx & 0xff);
+ if (!(edx >> 18))
+ printf("none/disabled\n");
+ else {
+ /* family 0x10 has shared L3 cache */
+ printf("Size: %uKb\t",
+ (edx >> 18) * 512);
+ do_l2assoc((edx >> 12) & 0x0f);
+ printf("\n\t");
+ printf("lines per tag=%u\t", (edx >> 8) & 0x0f);
+ printf("line size=%u bytes.\n", edx & 0xff);
+ }
}
}
@@ -356,7 +366,7 @@
amd_nameptr = cpu->name;
- if (cpu->maxi < 1)
+ if (cpu->cpuid_level < 1)
return;
if (cpu->family == 0xf) {
@@ -702,6 +712,19 @@
}
}
+static void show_patch_level(struct cpudata *cpu)
+{
+ unsigned long long val = 0;
+ if (!user_is_root)
+ return;
+
+ if (read_msr(cpu->number, 0x8b, &val) == 1) {
+ if (val>0)
+ printf("Microcode patch level: 0x%llx\n", val);
+ printf("\n");
+ }
+}
+
void display_AMD_info(struct cpudata *cpu)
{
unsigned int eax, ebx, ecx, edx;
@@ -713,8 +736,11 @@
dump_athlon_MSR(cpu);
}
- if (show_bluesmoke)
- decode_athlon_bluesmoke(cpu->number);
+ if (show_machine_check)
+ decode_athlon_machine_check(cpu->number);
+
+ if (show_microcode && family(cpu) >= 0xf)
+ show_patch_level(cpu);
if (show_pm)
decode_powernow(cpu);
@@ -722,7 +748,7 @@
if (show_bugs)
show_amd_bugs(cpu);
- if (cpu->maxi >= 0x05) {
+ if (cpu->cpuid_level >= 0x05) {
cpuid (cpu->number, 0x05, &eax, &ebx, &ecx, NULL);
printf("Monitor/Mwait: min/max line size %d/%d%s%s\n",
(int) (eax & 0xffff), (int) (ebx & 0xffff),
@@ -742,6 +768,18 @@
printf(", SVMLock");
if (edx & 8)
printf(", NRIPSave");
+ if (edx & 0x10)
+ printf(", TscRateMsr");
+ if (edx & 0x20)
+ printf(", VmcbClean");
+ if (edx & 0x40)
+ printf(", FlushByAsid");
+ if (edx & 0x80)
+ printf(", DecodeAssists");
+ if (edx & 0x400)
+ printf(", PauseFilter");
+ if (edx & 0x1000)
+ printf(", PauseFilterThreshold");
printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/k8.regs
^
|
| @@ -1,6 +1,6 @@
# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
#
-# Copyright (C) 2008 Advanced Micro Devices, Inc.
+# Copyright (C) 2008, 2009 Advanced Micro Devices, Inc.
# This file contains information from:
# - "26094 Rev 3.30 - February 2006, BIOS and Kernel Developer's Guide
@@ -38,6 +38,11 @@
:46
}
+{PATCH_LEVEL=0x008b;microcode patch level
+ PATCH_LEVEL:32
+ :32
+}
+
{MTRRcap=0x00fe;MTRR capabilities
MtrrCapVCnt:8
MtrrCapFix:1
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/AMD/machine_check.c
^
|
| @@ -0,0 +1,120 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Dump machine check registers.
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "AMD.h"
+
+#define MCG_CAP 0x0179
+#define MCG_STATUS 0x17a
+#define MCG_CTL 0x17b
+
+#define MC_CTL 0x0400
+#define MC_STATUS 0x0401
+#define MC_ADDR 0x402
+#define MC_MISC 0x403
+
+void decode_athlon_machine_check(int cpunum)
+{
+ unsigned long long val, val2;
+ unsigned int banks, i, ctlp = 0;
+
+ if (!user_is_root)
+ return;
+
+ if (read_msr(cpunum, MCG_CAP, &val) != 1)
+ return;
+
+ ctlp = val & (1<<8);
+ if (ctlp == 0)
+ printf("Erk, MCG_CTL not present! :%016llx:\n", val);
+
+ banks = val & 0xf;
+
+ printf("Number of reporting banks : %d\n\n", banks);
+
+ if (read_msr(cpunum, MCG_STATUS, &val) == 1) {
+ if (val != 0) {
+ printf(" 31 23 15 7 \n");
+ printf("MCG_STATUS: ");
+ dumpmsr_bin (cpunum, MCG_STATUS, 32);
+ }
+ }
+
+ if ( ctlp && read_msr(cpunum, MCG_CTL, &val) == 1) {
+ printf("MCG_CTL:\n");
+
+ printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
+ if ((val & (1<<0)) == 1) {
+ if (read_msr(cpunum, MC_CTL, &val2) == 1) {
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ }
+ }
+
+ printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
+ if (((val & (1<<1)) == 2) && (banks>1)) {
+ if (read_msr(cpunum, MC_CTL+4, &val2) == 1) {
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
+ printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
+ printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
+ }
+ }
+
+ printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
+ if ((val & (1<<2)) == 4 && (banks>2)) {
+ if (read_msr(cpunum, MC_CTL+8, &val2) == 1) {
+ printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ }
+ }
+
+ printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
+ if ((val & (1<<3)) == 8 && (banks>3)) {
+ if (read_msr(cpunum, MC_CTL+12, &val2) == 1) {
+ printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ }
+ }
+ }
+ printf("\n");
+
+
+ printf(" 31 23 15 7 \n");
+ for (i=0; i<banks; i++) {
+ printf("Bank: %u (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
+ printf("MC%uCTL: ", i);
+ dumpmsr_bin (cpunum, MC_CTL+i*4, 32);
+ printf("MC%uSTATUS: ", i);
+ dumpmsr_bin (cpunum, MC_STATUS+i*4, 32);
+ printf("MC%uADDR: ", i);
+ dumpmsr_bin (cpunum, MC_ADDR+i*4, 32);
+ printf("MC%uMISC: ", i);
+ dumpmsr_bin (cpunum, MC_MISC+i*4, 32);
+ printf("\n");
+ }
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/powernow.c
^
|
| @@ -9,6 +9,7 @@
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
+#include <pci/pci.h>
#include "../x86info.h"
#include "AMD.h"
#include "powernow.h"
@@ -117,21 +118,85 @@
k8_fid_codes[fidvidstatus.bits.cfid]);
}
-static int get_cof(int fid, int did, int family)
+static int get_did(int family, union msr_pstate pstate)
{
- int t = 0x10;
- if (family == 0x10)
- t = 0x10;
+ int t;
+
+ if (family == 0x14)
+ t = ((pstate.val >> 2) & 0x1f) + 4 + ((pstate.val & 0x3));
+ else if (family == 0x12)
+ t = pstate.val & 0xf;
else
+ t = pstate.bits.did;
+
+ return t;
+}
+
+static int get_cof(int family, union msr_pstate pstate)
+{
+ int t;
+ int fid, did;
+
+ did = get_did(family, pstate);
+
+ t = 0x10;
+ fid = pstate.bits.fid;
+ if (family == 0x11)
t = 0x8;
- return (100*(fid+t)>>did);
+
+ return ((100 * (fid + t)) >> did);
+ }
+
+static int get_num_boost_states(void)
+{
+ struct pci_filter filter_nb_link = { -1, -1, -1, -1, 0x1022, 0};
+ int dev_ids[3] = {0x1204};
+ struct pci_access *pacc;
+ struct pci_dev *z = NULL;
+ u8 val;
+ int i;
+
+ pacc = pci_alloc();
+ pci_init(pacc);
+ pci_scan_bus(pacc);
+
+ for (i=0; i<ARRAY_SIZE(dev_ids); i++) {
+ filter_nb_link.device = dev_ids[i];
+ for (z=pacc->devices; z; z=z->next) {
+ if (pci_filter_match(&filter_nb_link, z))
+ goto match;
+ }
+ }
+
+ match:
+ val = 0;
+ if (z) {
+ val = pci_read_byte(z, 0x15c);
+ if (val & 3)
+ printf("Boosting enabled\n");
+ else
+ printf("Boosting disabled\n");
+ val = (val >> 2) & 1;
+ printf("Number of boost states: %d\n", val);
+ }
+
+ pci_cleanup(pacc);
+ return val;
}
-static void decode_pstates(struct cpudata *cpu)
+static void decode_pstates(struct cpudata *cpu, int has_cpb)
{
- int i, psmax, pscur;
+ int i, psmax, pscur, fam;
union msr_pstate pstate;
unsigned long long val;
+ int boost_states = 0;
+
+ fam = family(cpu);
+ if (fam < 0x10)
+ return;
+
+ if (has_cpb)
+ boost_states = get_num_boost_states();
if (read_msr(cpu->number, MSR_PSTATE_LIMIT, &val) != 1) {
printf("Something went wrong reading MSR_PSTATE_CUR_LIMIT\n");
@@ -145,16 +210,21 @@
}
pscur = val & 0x7;
+ pscur += boost_states;
+ psmax += boost_states;
for (i=0; i<=psmax; i++) {
if (read_msr(cpu->number, MSR_PSTATE + i, &pstate.val) != 1) {
printf("Something went wrong reading MSR_PSTATE_%d\n",
i);
return;
}
- printf("Pstate-%d: fid=%x, did=%x, vid=%x (%dMHz)%s\n", i,
- pstate.bits.fid, pstate.bits.did, pstate.bits.vid,
- get_cof(pstate.bits.fid, pstate.bits.did, family(cpu)),
- (i == pscur) ? " (current)" : "");
+ if (i < boost_states)
+ printf("Pstate-Pb%d: %dMHz (boost state)\n",
+ i, get_cof(fam, pstate));
+ else
+ printf("Pstate-P%d: %dMHz%s\n",
+ i - boost_states, get_cof(fam, pstate),
+ (i == pscur) ? " (current)" : "");
}
printf("\n");
}
@@ -163,6 +233,7 @@
{
unsigned int eax, ebx, ecx, edx;
int can_scale_vid=0, can_scale_fid=0;
+ int has_cpb = 0;
if (cpu->maxei < 0x80000007)
return;
@@ -195,8 +266,19 @@
}
if (edx & (1<<8))
printf("\n\tinvariant TSC");
- if (!(edx & 0x1f))
+ if (edx & (1<<9)) {
+ printf("\n\tCore Performance Boost");
+ has_cpb = 1;
+ }
+ if (edx & (1<<10))
+ printf("\n\read-only Effective Frequency Interface");
+ if (!(edx & 0x1ff))
printf(" None");
+
+ cpuid(cpu->number, 6, &eax, &ebx, &ecx, &edx);
+ if (ecx & 1)
+ printf("\n\tEffective Frequency Interface");
+
printf("\n\n");
if (can_scale_fid==0 && can_scale_vid==0)
@@ -210,5 +292,5 @@
else if (family(cpu) == 0xf)
k8_decode_fidvid(cpu);
else if (family(cpu) >= 0x10)
- decode_pstates(cpu);
+ decode_pstates(cpu, has_cpb);
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/AMD/revision.h
^
|
| @@ -121,20 +121,25 @@
{0xc0f13, CONN_SOCKET_F, _ATHLON64_FX, "JH-F3"},
};
-#define _OPTERON 0x0001
-#define _PHENOM 0x0002
-
struct fam10h_rev {
int eax;
- int nameid;
const char* rev;
};
struct fam10h_rev fam10h_revisions[] = {
- {0x0100f2a, _OPTERON, "DR-BA"},
- {0x0100f22, _OPTERON|_PHENOM, "DR-B2"},
- {0x0100f23, _OPTERON|_PHENOM, "DR-B3"},
- {0x0100f42, _OPTERON, "RB-C2"},
+ {0x0100f2a, "DR-BA"},
+ {0x0100f22, "DR-B2"},
+ {0x0100f23, "DR-B3"},
+ {0x0100f42, "RB-C2"},
+ {0x0100f43, "RB-C3"},
+ {0x0100f52, "BL-C2"},
+ {0x0100f53, "BL-C3"},
+ {0x0100f62, "DA-C2"},
+ {0x0100f63, "DA-C3"},
+ {0x0100f80, "HY-D0"},
+ {0x0100f81, "HY-D1"},
+ {0x0100f91, "HY-D1"},
+ {0x0100fa0, "PH-E0"},
};
struct id_string fam11h_revisions[] = {
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Centaur/identify.c
^
|
| @@ -10,13 +10,11 @@
#include "centaur.h"
static char *centaur_nameptr;
-#define add_to_cpuname(x) centaur_nameptr += snprintf(centaur_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) centaur_nameptr += snprintf(centaur_nameptr, sizeof(x), "%s", x)
void identify_centaur(struct cpudata *cpu)
{
- char *nameptr;
-
- centaur_nameptr = nameptr = cpu->name;
+ centaur_nameptr = cpu->name;
switch (tuple(cpu) & 0xff0) {
case 0x540:
@@ -166,6 +164,6 @@
decode_centaur_cacheinfo(cpu);
- if (cpu->family == 6 && show_registers)
+ if (cpu->family == 6 && show_cpuid)
dump_C3_MSR(cpu);
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Cyrix/identify.c
^
|
| @@ -11,7 +11,7 @@
#include "Cyrix.h"
static char *cyrix_nameptr;
-#define add_to_cpuname(x) cyrix_nameptr += snprintf(cyrix_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) cyrix_nameptr += snprintf(cyrix_nameptr, sizeof(x), "%s", x)
/* Decode TLB and cache info descriptors */
void decode_Cyrix_TLB (int x)
@@ -79,7 +79,7 @@
unsigned int eax, ebx, ecx, edx;
printf("TLB & L1 Cache info\n");
- if (cpu->maxi >= 2 && show_cacheinfo) {
+ if (cpu->cpuid_level >= 2 && show_cacheinfo) {
/* TLB and L1 Cache info */
ntlb = 255;
for (i = 0; i < ntlb; i++) {
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/Intel.h
^
|
| @@ -2,11 +2,16 @@
#define _INTEL_H
extern void decode_Intel_caches (struct cpudata *cpu, int output);
extern void show_Intel_caches(struct cpudata *cpu);
-extern void decode_Intel_bluesmoke(int cpunum, int family);
+extern void decode_Intel_machine_check(int cpunum, int family);
+
extern void dump_p4_MSRs(struct cpudata *cpu);
extern void dump_p6_MSRs(struct cpudata *cpu);
-extern void dump_centrino_MSRs(struct cpudata *cpu);
+extern void dump_performance_MSRs(struct cpudata *cpu);
+extern void dump_thermal_MSRs(struct cpudata *cpu);
+extern void dump_IDA_MSRs(struct cpudata *cpu);
+
extern void decode_microcode(struct cpudata *cpu);
+
extern void Identify_Intel_family6pentium(struct cpudata *cpu);
extern void Identify_Intel_family6core(struct cpudata *cpu);
extern void Identify_Intel_family15(struct cpudata *cpu);
@@ -20,5 +25,6 @@
#define MSR_IA32_THERM_STATUS 0x19c
#define MSR_PM_THERM2_CTL 0x19d
#define MSR_IA32_MISC_ENABLE 0x1a0
+#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
#endif /* _INTEL_H */
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/Intel/MSR-IDA.c
^
|
| @@ -0,0 +1,57 @@
+/*
+ * (C) 2011 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+void dump_IDA_MSRs(struct cpudata *cpu)
+{
+ unsigned long long val = 0;
+ unsigned int eax, ebx, ecx, edx;
+
+ if (!user_is_root)
+ return;
+
+ if (cpu->cpuid_level < 6)
+ return;
+
+ cpuid(cpu->number, 6, &eax, &ebx, &ecx, &edx);
+
+ printf("Dynamic Acceleration MSRs:\n");
+ printf(" Opportunistic performance operation ");
+ if ((eax & (1 << 1)) == 1)
+ printf("enabled by BIOS\n");
+ else
+ printf("disabled by BIOS (or not supported)\n");
+
+ if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) != 1)
+ return;
+
+ if ((val & (1ULL << 38)) == 1) {
+ printf(" IA32_MISC_ENABLES[38] is 1 (disabled opportunistic performance operation)\n");
+ return;
+ }
+
+ if (read_msr(cpu->number, MSR_IA32_PERF_CTL, &val) != 1)
+ return;
+ printf(" IA32_PERF_CTL: ");
+ if ((val & (1ULL << 32)) == 1) {
+ printf("IDA/Turbo DISENGAGE=1, ");
+ }
+ printf("EIST Transition target: 0x%x\n", (unsigned int) val & 0xff);
+
+
+ if (ecx & (1 << 3)) { /* SETBH present ? */
+ if (read_msr(cpu->number, MSR_IA32_ENERGY_PERF_BIAS, &val) != 1)
+ return;
+ printf(" IA32_ENERGY_PERF_BIAS: ");
+ printf("hint=%d\n", (unsigned int) val & 0xf);
+ }
+}
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/Intel/MSR-performance.c
^
|
| @@ -0,0 +1,44 @@
+/*
+ * (C) 2011 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+void dump_performance_MSRs(struct cpudata *cpu)
+{
+ unsigned long long val = 0;
+
+ if (!user_is_root)
+ return;
+
+ printf("Performance MSRs:\n");
+ if (read_msr(cpu->number, MSR_IA32_PERF_STATUS, &val) == 1)
+ printf(" MSR_IA32_PERF_STATUS: 0x%llx\n", val);
+
+ if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) == 1) {
+ printf(" MSR_IA32_MISC_ENABLE: 0x%llx", val);
+ printf(" [Enabled: ");
+ if (val & (1<<3))
+ printf("TCC ");
+ if (val & (1<<7))
+ printf("PerfMon ");
+ if (val & (1<<10))
+ printf("FERR# ");
+ if (val & (1<<11))
+ printf("noBTS ");
+ if (val & (1<<12))
+ printf("noPEBS ");
+ if (val & (1<<16))
+ printf("EnhancedSpeedStep ");
+
+ printf("]\n");
+ }
+ printf("\n");
+}
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/Intel/MSR-thermal.c
^
|
| @@ -0,0 +1,54 @@
+/*
+ * (C) 2011 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+void dump_thermal_MSRs(struct cpudata *cpu)
+{
+ unsigned long long val = 0;
+
+ if (!user_is_root)
+ return;
+
+ if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) != 1)
+ return;
+
+ // tcc enabled ?
+ if (!(val & (1<<3)))
+ return;
+
+ printf("Thermal MSRs:\n");
+ if (read_msr(cpu->number, MSR_PM_THERM2_CTL, &val) == 1) { /* THERM2_CTL */
+ printf(" MSR_PM_THERM2_CTL: 0x%llx [Thermal monitor: %d]\n",
+ val, (val & (1<<16)) ? 2 : 1);
+ }
+ if (read_msr(cpu->number, MSR_IA32_THERM_CONTROL, &val) == 1) {
+ printf(" MSR_IA32_THERM_CONTROL: 0x%llx ", val);
+ if (val & (1<<4)) {
+ printf("[Software-controlled clock: %f%% duty cycle]\n",
+ ((val >> 1) & 7) / 8.);
+ } else
+ printf("[Software-controlled clock disabled (full speed)]\n");
+ }
+ if (read_msr (cpu->number, MSR_IA32_THERM_STATUS, &val) == 1) { /* THERM_STATUS */
+ printf(" MSR_IA32_THERM_STATUS: 0x%llx", val);
+ if (val & (1<<0|1<<1)) {
+ printf(" [");
+ if (val & (1<<0))
+ printf("TooHot ");
+ if (val & (1<<1))
+ printf("WasTooHot ");
+ printf("]");
+ }
+ printf("\n");
+ }
+ printf("\n");
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/cachesize.c
^
|
| @@ -1,13 +1,12 @@
/*
- * (C) 2001 Dave Jones.
+ * (C) 2001-2011 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
* Intel specific parts
*
* References:
- * http://developer.intel.com/
- * http://microcodes.sourceforge.net/CPUID.htm
+ * http://www.intel.com/Assets/PDF/appnote/241618.pdf
*/
#include <stdio.h>
@@ -15,6 +14,8 @@
#include "../x86info.h"
#include "Intel.h"
+#define MB(x) ((x) * 1024)
+
struct _cache_table
{
unsigned char descriptor;
@@ -45,6 +46,7 @@
{ 0xa, 8, "L1 Data cache: 8KB, 2-way associative. 32 byte line size." },
{ 0xc, 16, "L1 Data cache: 16KB, 4-way associative. 32 byte line size." },
{ 0xd, 16, "L1 Data cache: 16KB, 4-way associative. 64 byte line size. ECC." },
+ { 0xe, 24, "L1 Data cache: 24KB, 6-way associative. 64 byte line size. ECC." },
{ 0x2c, 32, "L1 Data cache: 32KB, 8-way associative. 64 byte line size." },
{ 0x60, 16, "L1 Data cache: 16KB, sectored, 8-way associative. 64 byte line size." },
{ 0x66 , 8, "L1 Data cache: 8KB, sectored, 4-way associative. 64 byte line size." },
@@ -57,78 +59,83 @@
{
{ 0x21, 256, "L2 (MLC): 256KB, 8-way associative. 64 byte line size." },
{ 0x39, 128, "L2 cache: 128KB, 4-way associative. Sectored. 64 byte line size." },
- { 0x3a, 192, "L2 cache: 192KB, 6-way associative. Sectored. 64 byte line size." },
+/* { 0x3a, 192, "L2 cache: 192KB, 6-way associative. Sectored. 64 byte line size." },
{ 0x3b, 128, "L2 cache: 128KB, 2-way associative. Sectored. 64 byte line size." },
{ 0x3c, 256, "L2 cache: 256KB, 4-way associative. Sectored. 64 byte line size." },
{ 0x3d, 384, "L2 cache: 384KB, 6-way associative. Sectored. 64 byte line size." },
{ 0x3e, 512, "L2 cache: 512KB, 4-way associative. Sectored. 64 byte line size." },
-/* { 0x3f, 256, "L2 cache: 256KB, 2-way associative. Sectored. 64 byte line size." }, */
-/* 3f is no longer listed. */
+ { 0x3f, 256, "L2 cache: 256KB, 2-way associative. Sectored. 64 byte line size." }, */
+/* 3a->3f are no longer listed. */
{ 0x41, 128, "L2 cache: 128KB, 4-way associative. 32 byte line size." },
{ 0x42, 256, "L2 cache: 256KB, 4-way associative. 32 byte line size." },
{ 0x43, 512, "L2 cache: 512KB, 4-way associative. 32 byte line size." },
- { 0x44, 1024, "L2 cache: 1MB, 4-way associative. 32 byte line size." },
- { 0x45, 2048, "L2 cache: 2MB, 4-way associative. 32 byte line size." },
- { 0x48, 3072, "L2 cache: 3MB, 12-way associative. 64 byte line size. Unified on-die." },
- { 0x4e, 6144, "L2 cache: 6MB, 24-way set associative, 64-byte line size." },
+ { 0x44, MB(1), "L2 cache: 1MB, 4-way associative. 32 byte line size." },
+ { 0x45, MB(2), "L2 cache: 2MB, 4-way associative. 32 byte line size." },
+ { 0x48, MB(3), "L2 cache: 3MB, 12-way associative. 64 byte line size. Unified on-die." },
+ { 0x4e, MB(6), "L2 cache: 6MB, 24-way set associative, 64-byte line size." },
{ 0x79, 128, "L2 cache: 128KB, sectored, 8-way associative. 64 byte line size." },
{ 0x7a, 256, "L2 cache: 256KB, sectored, 8-way associative. 64 byte line size." },
{ 0x7b, 512, "L2 cache: 512KB, sectored, 8-way associative. 64 byte line size." },
- { 0x7c, 1024, "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
- { 0x7d, 2048, "L2 cache: 2MB, 8-way associative. 64 byte line size." },
+ { 0x7c, MB(1), "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0x7d, MB(2), "L2 cache: 2MB, 8-way associative. 64 byte line size." },
{ 0x7f, 512, "L2 cache: 512KB, 2-way associative. 64 byte line size." },
+ { 0x80, 512, "L2 cache: 512KB, 8-way associative. 64 byte line size." },
{ 0x82, 256, "L2 cache: 256KB, 8-way associative. 32 byte line size." },
{ 0x83, 512, "L2 cache: 512KB, 8-way associative. 32 byte line size." },
- { 0x84, 1024, "L2 cache: 1MB, 8-way associative. 32 byte line size." },
- { 0x85, 2048, "L2 cache: 2MB, 8-way associative. 32 byte line size." },
+ { 0x84, MB(1), "L2 cache: 1MB, 8-way associative. 32 byte line size." },
+ { 0x85, MB(2), "L2 cache: 2MB, 8-way associative. 32 byte line size." },
{ 0x86, 512, "L2 cache: 512KB, 4-way associative. 64 byte line size." },
- { 0x87, 1024, "L2 cache: 1MB, 8-way associative. 64 byte line size." },
+ { 0x87, MB(1), "L2 cache: 1MB, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L2L3_cache_table[] =
{
- { 0x46, 4096, "L2 cache: 4MB, 4-way associative. 64 byte line size." },
- { 0x47, 8192, "L2 cache: 8MB, 8-way associative. 64 byte line size." },
- { 0x49, 4096, "L2 cache: 4MB, 16-way associative. 64 byte line size." },
- { 0x4a, 6144, "L2 cache: 6MB, 12-way associative. 64 byte line size." },
- { 0x4b, 8192, "L2 cache: 8MB, 16-way associative. 64 byte line size." },
- { 0x4c, 12288, "L2 cache: 12MB, 12-way associative. 64 byte line size." },
- { 0x4d, 16384, "L2 cache: 16MB, 16-way associative. 64 byte line size." },
- { 0x78, 1024, "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0x46, MB(4), "L2 cache: 4MB, 4-way associative. 64 byte line size." },
+ { 0x47, MB(8), "L2 cache: 8MB, 8-way associative. 64 byte line size." },
+ { 0x48, MB(3), "L2 cache: 3MB, 12-way associative. 64 byte line size." },
+ { 0x49, MB(4), "L2 cache: 4MB, 16-way associative. 64 byte line size." },
+ { 0x4a, MB(6), "L2 cache: 6MB, 12-way associative. 64 byte line size." },
+ { 0x4b, MB(8), "L2 cache: 8MB, 16-way associative. 64 byte line size." },
+ { 0x4c, MB(12), "L2 cache: 12MB, 12-way associative. 64 byte line size." },
+ { 0x4d, MB(16), "L2 cache: 16MB, 16-way associative. 64 byte line size." },
+ { 0x78, MB(1), "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L3L2_cache_table[] =
{
- { 0x46, 4096, "L3 cache: 4MB, 4-way associative. 64 byte line size." },
- { 0x47, 8192, "L3 cache: 8MB, 8-way associative. 64 byte line size." },
- { 0x49, 4096, "L3 cache: 4MB, 16-way associative. 64 byte line size." },
- { 0x4a, 6144, "L3 cache: 6MB, 12-way associative. 64 byte line size." },
- { 0x4b, 8192, "L3 cache: 8MB, 16-way associative. 64 byte line size." },
- { 0x4c, 12288, "L3 cache: 12MB, 12-way associative. 64 byte line size." },
- { 0x4d, 16384, "L3 cache: 16MB, 16-way associative. 64 byte line size." },
- { 0x78, 1024, "L3 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
+ { 0x46, MB(4), "L3 cache: 4MB, 4-way associative. 64 byte line size." },
+ { 0x47, MB(8), "L3 cache: 8MB, 8-way associative. 64 byte line size." },
+ { 0x49, MB(4), "L3 cache: 4MB, 16-way associative. 64 byte line size." },
+ { 0x4a, MB(6), "L3 cache: 6MB, 12-way associative. 64 byte line size." },
+ { 0x4b, MB(8), "L3 cache: 8MB, 16-way associative. 64 byte line size." },
+ { 0x4c, MB(12), "L3 cache: 12MB, 12-way associative. 64 byte line size." },
+ { 0x4d, MB(16), "L3 cache: 16MB, 16-way associative. 64 byte line size." },
+ { 0x78, MB(1), "L3 cache: 1MB, sectored, 8-way associative. 64 byte line size." },
{ 0xd0, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." },
- { 0xd1, 1024, "L3 cache: 1MB, 4-way associative. 64 byte line size." },
- { 0xd2, 2048, "L3 cache: 2MB, 4-way associative. 64 byte line size." },
- { 0xd6, 1024, "L3 cache: 1MB, 8-way associative. 64 byte line size." },
- { 0xd7, 2048, "L3 cache: 2MB, 8-way associative. 64 byte line size." },
- { 0xd8, 4096, "L3 cache: 4MB, 8-way associative. 64 byte line size." },
- { 0xdc, 2048, "L3 cache: 2MB, 12-way associative. 64 byte line size." },
- { 0xdd, 4096, "L3 cache: 4MB, 12-way associative. 64 byte line size." },
- { 0xe2, 2048, "L3 cache: 2MB, 16-way associative. 64 byte line size." },
- { 0xe3, 4096, "L3 cache: 4MB, 16-way associative. 64 byte line size." },
- { 0xe4, 8192, "L3 cache: 8MB, 16-way associative. 64 byte line size." },
- { 0xde, 8192, "L3 cache: 8MB, 12-way associative. 64 byte line size." },
+ { 0xd1, MB(1), "L3 cache: 1MB, 4-way associative. 64 byte line size." },
+ { 0xd2, MB(2), "L3 cache: 2MB, 4-way associative. 64 byte line size." },
+ { 0xd6, MB(1), "L3 cache: 1MB, 8-way associative. 64 byte line size." },
+ { 0xd7, MB(2), "L3 cache: 2MB, 8-way associative. 64 byte line size." },
+ { 0xd8, MB(4), "L3 cache: 4MB, 8-way associative. 64 byte line size." },
+ { 0xdc, MB(2), "L3 cache: 2MB, 12-way associative. 64 byte line size." },
+ { 0xdd, MB(4), "L3 cache: 4MB, 12-way associative. 64 byte line size." },
+ { 0xe2, MB(2), "L3 cache: 2MB, 16-way associative. 64 byte line size." },
+ { 0xe3, MB(4), "L3 cache: 4MB, 16-way associative. 64 byte line size." },
+ { 0xe4, MB(8), "L3 cache: 8MB, 16-way associative. 64 byte line size." },
+ { 0xea, MB(12), "L3 cache: 12MB, 24-way associative. 64 byte line size." },
+ { 0xeb, MB(18), "L3 cache: 18MB, 24-way associative. 64 byte line size." },
+ { 0xec, MB(24), "L3 cache: 24MB, 24-way associative. 64 byte line size." },
+ { 0xde, MB(8), "L3 cache: 8MB, 12-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
static struct _cache_table L3_cache_table[] =
{
{ 0x22, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." },
- { 0x23, 1024, "L3 cache: 1MB, 8-way associative. 64 byte line size." },
- { 0x25, 2048, "L3 cache: 2MB, 8-way associative. 64 byte line size." },
- { 0x29, 4096, "L3 cache: 4MB, 8-way associative. 64 byte line size." },
+ { 0x23, MB(1), "L3 cache: 1MB, 8-way associative. 64 byte line size." },
+ { 0x25, MB(2), "L3 cache: 2MB, 8-way associative. 64 byte line size." },
+ { 0x29, MB(4), "L3 cache: 4MB, 8-way associative. 64 byte line size." },
{ 0, 0, NULL }
};
@@ -139,8 +146,10 @@
{ 0x50, 64, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries." },
{ 0x51, 128, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries." },
{ 0x52, 256, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 256 entries." },
+ { 0x55, 7, "Instruction TLB: 2MB or 4MB pages, fully associative, 7 entries" },
{ 0xb0, 128, "Instruction TLB: 4K pages, 4-way associative, 128 entries." },
{ 0xb1, 4, "Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative" },
+ { 0xb2, 64, "Instruction TLB: 4K pages, 4-way associative, 64 entries." },
{ 0, 0, NULL }
};
@@ -151,11 +160,13 @@
{ 0x5, 32, "Data TLB: 4MB pages, 4-way associative, 32 entries" },
{ 0x56, 16, "L1 Data TLB: 4MB pages, 4-way set associative, 16 entries" },
{ 0x57, 16, "L1 Data TLB: 4KB pages, 4-way set associative, 16 entries" },
+ { 0x5a, 32, "Data TLB: 4KB or 4MB pages, fully associative, 32 entries." },
{ 0x5b, 64, "Data TLB: 4KB or 4MB pages, fully associative, 64 entries." },
{ 0x5c, 128, "Data TLB: 4KB or 4MB pages, fully associative, 128 entries." },
{ 0x5d, 256, "Data TLB: 4KB or 4MB pages, fully associative, 256 entries." },
{ 0xb3, 128, "Data TLB: 4K pages, 4-way associative, 128 entries." },
{ 0xb4, 256, "Data TLB: 4K pages, 4-way associative, 256 entries." },
+ { 0xca, 512, "Data TLB: 4K pages, 4-way associative, 512 entries." },
{ 0, 0, NULL }
};
@@ -266,7 +277,7 @@
unsigned int i = 0;
unsigned char oldknown;
- if (cpu->maxi < 2)
+ if (cpu->cpuid_level < 2)
return;
memset(&unknown_array, 0, sizeof(unknown_array));
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/identify-family15.c
^
|
| @@ -16,7 +16,7 @@
static char p4_errata[]="http://developer.intel.com/design/pentium4/specupdt/249199.htm";
static char *intel_nameptr;
-#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x)
void Identify_Intel_family15(struct cpudata *cpu)
{
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/identify-family6-extended.c
^
|
| @@ -12,8 +12,10 @@
#include "../x86info.h"
#include "Intel.h"
+static char nehalem_info_url[] = "http://www.intel.com/design/corei7/documentation.htm";
+
static char *intel_nameptr;
-#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x)
void Identify_Intel_family6core(struct cpudata *cpu)
{
@@ -158,25 +160,29 @@
* sSpec step TDP Name FSB EFMS HFM LFM Package
*
*
- * SLB6Q C0 0.65W Z500 400 106C2 0.8GHz 600Mhz FCBGA8
- * SLB2C C0 2W Z510 400 106C2 1.1GHz 600Mhz FCBGA8
- * SLB2H C0 2W Z520 533 106C2 1.33GHz 800Mhz FCBGA8
- * SLB6P C0 2W Z530 533 106C2 1.60GHz 800Mhz FCBGA8
+ * SLB6Q C0 0.65W Z500 400 106C2 800GHz 600MHz FCBGA8
+ * SLB2C C0 2W Z510 400 106C2 1.1GHz 600MHz FCBGA8
+ * SLGMG C0 0.65W Z515 400 106C2 800MHz 600MHz FCBGA8
+ * SLB2H C0 2W Z520 533 106C2 1.33GHz 800MHz FCBGA8
+ * SLB6P C0 2W Z530 533 106C2 1.60GHz 800MHz FCBGA8
* QGZT C0 2.5W N270 533 106C2 1.60GHz 800MHz FCBGA8
- * QKGY1 C0 8W 300 533 106C2 1.60GHz ------ FCBGA 437
- * QGZR2 C0 4W 230 533 106C2 1.60GHz ----- FCBGA437 M01106C2208
- * SLB2M C0 2.4W Z540 533 106C2 1.86GHz 800Mhz FCBGA8
+ * QKGY1 C0 8W 300 533 106C2 1.60GHz ------ FCBGA437
+ * QGZR2 C0 4W 230 533 106C2 1.60GHz ----- FCBGA437
+ * SLB2M C0 2.4W Z540 533 106C2 1.86GHz 800MHz FCBGA8
+ * SLGPT C0 2.4W Z550 533 106C2 2.0GHz 800MHz FCBGA8
*/
switch (cpu->MHz) {
- case 800: add_to_cpuname("Z500 [SLB6Q][C0]")
+ case 800: add_to_cpuname("Z500/Z515 [SLB6Q/SLGMG][C0]");
break;
- case 1100: add_to_cpuname("Z510 [SLB2C][C0]")
+ case 1100: add_to_cpuname("Z510 [SLB2C][C0]");
break;
- case 1330: add_to_cpuname("Z520 [SLB2H][C0]")
+ case 1330: add_to_cpuname("Z520 [SLB2H][C0]");
break;
case 1600: // could be a Z530,an N270,a QKGY1 or a QGZR2
break;
- case 1860: add_to_cpuname("Z540 [SLB2M][C0]")
+ case 1860: add_to_cpuname("Z540 [SLB2M][C0]");
+ break;
+ case 2000: add_to_cpuname("Z550 [SLGPT][C0]");
break;
}
break;
@@ -235,7 +241,7 @@
}
break;
- case 23:
+ case 0x17:
add_to_cpuname("Core 2 Duo ");
switch (cpu->stepping) {
case 4: add_to_cpuname("(Penryn)");
@@ -245,13 +251,14 @@
}
break;
- case 26:
+ case 0x1a:
/*
* SLBCJ C-0 0x000106A4 3.20 / 6.40/ 1066 8MB
* SLBCK C-0 0x000106A4 2.93 / 4.80/ 1066 8MB
* SLBCH C-0 0x000106A4 2.66 / 4.80/ 1066 8MB
*/
- add_to_cpuname("Core i7 (Nehalem)");
+ add_to_cpuname("Core i7 (Nehalem) [bloomfield/gainestown]");
+ cpu->info_url = strdup(nehalem_info_url);
switch (cpu->MHz) {
case 3200: add_to_cpuname(" [C-0][SLBCJ]");
break;
@@ -262,6 +269,29 @@
}
break;
+ case 0x1c:
+ add_to_cpuname("Atom");
+ switch (cpu->stepping) {
+ case 10: add_to_cpuname(" D510");
+ break;
+ }
+ break;
+
+ case 0x1e:
+ add_to_cpuname("Core i7 (Nehalem) [Lynnfield/Clarksfield/Jasper Forest]");
+ break;
+
+ case 0x25:
+ add_to_cpuname("Core i7 (Nehalem) [Clarkdale/Arrandale]");
+ break;
+
+ case 0x2c:
+ add_to_cpuname("Core i7 (Nehalem) [Gulftown/Westmere-EP]");
+ break;
+
+ case 0x2e:
+ add_to_cpuname("Core i7 (Nehalem) [Beckton]");
+ break;
default:
add_to_cpuname("Unknown model. ");
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/identify-family6.c
^
|
| @@ -11,8 +11,10 @@
#include "../x86info.h"
#include "Intel.h"
+static char pm_90nm_info_url[] = "http://www.intel.com/design/intarch/pentiumm/docs_pentiumm_90nm.htm";
+
static char *intel_nameptr;
-#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x)
void Identify_Intel_family6pentium(struct cpudata *cpu)
{
@@ -500,6 +502,7 @@
SL89Y 738 1.4GHz 600MHz
*/
case 8: add_to_cpuname("(Dothan) [C-0]");
+ cpu->info_url = strdup(pm_90nm_info_url);
break;
}
break;
@@ -520,7 +523,7 @@
add_to_cpuname("Duo [L2]");
break;
case 5:
- add_to_cpuname("Duo ");
+ add_to_cpuname("Duo (Conroe XE)");
break;
case 6:
/*
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/identify.c
^
|
| @@ -16,7 +16,7 @@
#include "Intel.h"
static char *intel_nameptr;
-#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x)
void Identify_Intel(struct cpudata *cpu)
{
@@ -38,7 +38,7 @@
/* Figure out number of cores on this package. */
cpu->nr_cores = 1;
- if (cpu->maxi >= 4) {
+ if (cpu->cpuid_level >= 4) {
cpuid4(cpu->number, 0, &eax, &ebx, &ecx, &edx);
if (eax & 0x1f)
cpu->nr_cores = ((eax >> 26) + 1);
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/info.c
^
|
| @@ -22,7 +22,7 @@
unsigned int eax, ebx, ecx, edx;
unsigned int signature;
- if (cpu->maxi < 3)
+ if (cpu->cpuid_level < 3)
return;
cpuid(cpu->number, 1, &eax, NULL, NULL, NULL);
@@ -39,23 +39,10 @@
printf("Processor serial: %s\n", cpu->serialno);
}
-void display_Intel_info(struct cpudata *cpu)
+static void decode_brand(struct cpudata *cpu)
{
- printf("Type: %u (", cpu->type);
- switch (cpu->type) {
- case 0: printf("Original OEM");
- break;
- case 1: printf("Overdrive");
- break;
- case 2: printf("Dual-capable");
- break;
- case 3: printf("Reserved");
- break;
- }
printf(")\tBrand: %u (", cpu->brand);
switch (cpu->brand) {
- case 0: printf("Unsupported");
- break;
case 1:
case 0xA:
case 0x14: printf("Intel® Celeron® processor");
@@ -107,12 +94,38 @@
break;
}
printf(")\n");
+}
+void display_basic_Intel_info(struct cpudata *cpu)
+{
+ if (cpu->type != 3) {
+ printf("Type: %u (", cpu->type);
+ switch (cpu->type) {
+ case 0: printf("Original OEM");
+ break;
+ case 1: printf("Overdrive");
+ break;
+ case 2: printf("Dual-capable");
+ break;
+ }
+ printf(")\n");
+ }
+ if (cpu->brand > 0)
+ decode_brand(cpu);
+}
+
+
+void display_extended_Intel_info(struct cpudata *cpu)
+{
if (show_msr) {
if (cpu->family == 0xf)
dump_p4_MSRs(cpu);
- if (cpu->family == 0x6 && (cpu->model == 9 || cpu->model == 13))
- dump_centrino_MSRs(cpu);
+
+ dump_performance_MSRs(cpu);
+
+ dump_thermal_MSRs(cpu);
+
+// dump_IDA_MSRs(cpu);
}
if (show_eblcr) {
@@ -124,11 +137,9 @@
}
/* FIXME: Bit test for MCA here!*/
- if (show_bluesmoke)
- decode_Intel_bluesmoke(cpu->number, cpu->family);
+ if (show_machine_check)
+ decode_Intel_machine_check(cpu->number, cpu->family);
if (show_microcode)
decode_microcode(cpu);
-
- show_intel_topology(cpu);
}
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/Intel/machine_check.c
^
|
| @@ -0,0 +1,127 @@
+/*
+ * (C) 2001 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * Dump machine check registers.
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+#define MCG_CAP 0x0179
+#define MCG_CTL_PBIT 8
+#define MCG_EXT_PBIT 9
+#define MCG_STATUS 0x17a
+#define MCG_CTL 0x17b
+#define MCG_EXT 0x180
+
+#define MC_CTL 0x0400
+#define MC_STATUS 0x0401
+#define MC_ADDR 0x402
+
+static int nr_msr_banks;
+
+static void decode_mcg_ctl(int cpunum)
+{
+ unsigned long long val, val2;
+
+ if (read_msr(cpunum, MCG_CTL, &val) == 1) {
+ printf("MCG_CTL:\n");
+
+ printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis");
+ if ((val & (1<<0)) == 1) {
+ if (read_msr(cpunum, MC_CTL, &val2) == 1) {
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ }
+ }
+
+ printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis");
+ if (((val & (1<<1)) == 2) && (nr_msr_banks>1)) {
+ if (read_msr(cpunum, MC_CTL+4, &val2) == 1) {
+ printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis");
+ printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis");
+ printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis");
+ }
+ }
+
+ printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis");
+ if ((val & (1<<2)) == 4 && (nr_msr_banks>2)) {
+ if (read_msr(cpunum, MC_CTL+8, &val2) == 1) {
+ printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis");
+ printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis");
+ printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis");
+ printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis");
+ printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis");
+ }
+ }
+
+ printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis");
+ if ((val & (1<<3)) == 8 && (nr_msr_banks>3)) {
+ if (read_msr(cpunum, MC_CTL+12, &val2) == 1) {
+ printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis");
+ printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis");
+ }
+ }
+ }
+ printf("\n");
+}
+
+
+void decode_Intel_machine_check(int cpunum, int family)
+{
+ unsigned long long val;
+ int i, extcount = 0;
+
+ if (!user_is_root)
+ return;
+
+ if (read_msr(cpunum, MCG_CAP, &val) != 1)
+ return;
+
+ nr_msr_banks = val & 0xff;
+
+ printf("Machine check MSRs:\n");
+ printf("Number of reporting banks : %d\n", nr_msr_banks);
+
+ if (family == 0xf) {
+ if ((val & (1<<MCG_EXT_PBIT))) {
+ extcount = (val >> 16) & 0xff;
+ printf("Number of extended MC registers : %d\n\n", extcount);
+ }
+ else
+ printf("Erk, MCG_EXT not present! :%016llx:\n", val);
+ }
+ else
+ if (val & (1<<MCG_CTL_PBIT))
+ decode_mcg_ctl(cpunum);
+
+ for (i=0; i < nr_msr_banks; i++) {
+ printf("Bank: %d (0x%x)\n", i, (unsigned int)MC_CTL+i*4);
+ printf("MC%dCTL: ", i);
+ dumpmsr_bin (cpunum, MC_CTL+i*4, 64);
+ printf("MC%dSTATUS: ", i);
+ dumpmsr_bin (cpunum, MC_STATUS+i*4, 64);
+ printf("MC%dADDR: ", i);
+ dumpmsr_bin (cpunum, MC_ADDR+i*4, 64);
+ }
+ printf("\n");
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Intel/topology.c
^
|
| @@ -49,70 +49,86 @@
return r;
}
-
-/* Determine the width of the bit field that can represent the value item. */
-static unsigned int find_maskwidth(unsigned int item)
+static int get_count_order(unsigned int count)
{
- unsigned int MaskWidth = 0;
+ int order;
- MaskWidth = fls(item)-1;
- return MaskWidth;
+ order = fls(count) - 1;
+ if (count & (count - 1))
+ order++;
+ return order;
}
-/* Extract the subset of bit field from the 8-bit value FullID. It returns the 8-bit sub ID value */
-static unsigned char GetSubID(unsigned char FullID, unsigned char MaxSubIDvalue, unsigned char ShiftCount)
+static int intel_num_cpu_cores(struct cpudata *cpu)
{
- unsigned int MaskWidth, MaskBits, SubID;
+ unsigned int eax, ebx, ecx, edx;
+
+ if (cpu->cpuid_level < 4)
+ return 1;
- MaskWidth = find_maskwidth(MaxSubIDvalue);
- MaskBits = ((unsigned char) (0xff << ShiftCount)) ^ ((unsigned char) (0xff << (ShiftCount + MaskWidth))) ;
- SubID = (FullID & MaskBits) >> ShiftCount;
- return SubID;
+ /* Intel has a non-standard dependency on %ecx for this CPUID level. */
+ cpuid_count(cpu->number, 4, 0, &eax, &ebx, &ecx, &edx);
+ if (eax & 0x1f)
+ return (eax >> 26) + 1;
+ else
+ return 1;
}
+static int phys_pkg_id(int cpuid_apic, int index_msb)
+{
+ return cpuid_apic >> index_msb;
+}
-void show_intel_topology(struct cpudata *cpu)
+void get_intel_topology(struct cpudata *cpu)
{
unsigned int eax, ebx, ecx, edx;
- unsigned int MaxLPPerCore;
- unsigned int smt_id, core_id, package_id;
- unsigned int shift;
-
- cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx);
-
- /* Find the max number of logical processors per physical package. */
- if (cpu->flags_edx & (1 << 28))
- cpu->nr_logical = (ebx >> 16) & 0xff;
- else
- cpu->nr_logical = 1;
+ unsigned int index_msb, core_bits;
- /* Find the max number of processor cores per physical processor package. */
- if (cpu->maxi >= 4) {
- cpuid4(cpu->number, 0, &eax, &ebx, &ecx, &edx);
- if (eax & 0x1f)
- cpu->nr_cores = ((eax >> 26) + 1);
- } else {
- cpu->nr_cores = 1;
+ if (!(cpu->flags_edx & X86_FEATURE_HT))
+ return;
+/*
+ if (cpu_has(cpu, X86_FEATURE_CMP_LEGACY))
+ goto out;
+
+ if (cpu_has(cpu, X86_FEATURE_XTOPOLOGY))
+ return;
+*/
+
+
+ cpuid(cpu->number, 1, &eax, &ebx, &ecx, &edx);
+ cpu->num_siblings = (ebx & 0xff0000) >> 16;
+
+ if (cpu->num_siblings == 1) {
+ if (debug)
+ printf("Hyper-Threading is disabled\n");
+ goto out;
}
- //MaxLPPerCore = MaxLogicalProcPerPhysicalProc() / MaxCorePerPhysicalProc();
- MaxLPPerCore = cpu->nr_logical / cpu->nr_cores;
- printf("Number of cores per physical package=%d\n", cpu->nr_cores); // 8
- printf("Number of logical processors per socket=%d\n", cpu->nr_logical); // 16
- printf("Number of logical processors per core=%d\n", MaxLPPerCore); // 2
-
- /* test for hyperthreading. */
- if (cpu->flags_edx & (1 << 28)) {
- // test that there's more logical processor IDs with the same physical ID
- // than the number of cores per physical processors.
- }
+ if (cpu->num_siblings <= 1)
+ goto out;
- smt_id = GetSubID(cpu->apicid, cpu->nr_logical, 0);
- shift = find_maskwidth(cpu->nr_logical);
- core_id = GetSubID(cpu->apicid, cpu->nr_cores, shift);
- shift += find_maskwidth(cpu->nr_cores);
- package_id = GetSubID(cpu->apicid, MaxLPPerCore, shift);
-
- printf("APIC ID: 0x%x\t", cpu->apicid);
- printf("Package: %u Core: %u SMT ID %u\n", package_id, core_id, smt_id);
+ index_msb = get_count_order(cpu->num_siblings);
+ cpu->initial_apicid = (cpuid_ebx(cpu->number, 1) >> 24) & 0xFF;
+ cpu->phys_proc_id = phys_pkg_id(cpu->initial_apicid, index_msb);
+
+ cpu->x86_max_cores = intel_num_cpu_cores(cpu);
+ cpu->num_siblings = cpu->num_siblings / cpu->x86_max_cores;
+
+ index_msb = get_count_order(cpu->num_siblings);
+
+ core_bits = get_count_order(cpu->x86_max_cores);
+
+ cpu->cpu_core_id = phys_pkg_id(cpu->apicid, index_msb) &
+ ((1 << core_bits) - 1);
+
+ if (debug == 1) {
+ if ((cpu->x86_max_cores * cpu->num_siblings) > 1) {
+ printf("%s:\n", __func__);
+ printf("\tSiblings: %d\n", cpu->num_siblings);
+ printf("\tPhysical Processor ID: %d\n", cpu->phys_proc_id);
+ printf("\tProcessor Core ID: %d\n", cpu->cpu_core_id);
+ }
+ }
+out:
+ return;
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/Makefile
^
|
| @@ -1,98 +1,95 @@
+VERSION=1.29
+
CFLAGS = -g -O2 -Werror -Wall -Wshadow -Wextra -Wmissing-declarations -Wdeclaration-after-statement -Wredundant-decls
+LDFLAGS = -Wl,-z,relro,-z,now
CC = gcc
SHELL = /bin/sh
-
-.c.o:
- $(CC) $(CFLAGS) -MMD -o $@ -c $<
- @cp $*.d $*.P; \
- sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
- -e '/^$$/ d' -e 's/$$/ :/' < $*.d >> $*.P; \
- rm -f $*.d
-
-.S.o:
- $(CC) $(CFLAGS) -o $@ -c $<
-
-
all: x86info test lsmsr
-LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h generic_msr.h
+LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h AMD/fam11h.h generic_msr.h
%.h: %.regs scripts/createheader.py
python scripts/createheader.py $< `basename $< .regs` >$@
-LSMSR_SRC =\
- lsmsr.c\
- cpuid.c\
+LSMSR_SRC = \
+ lsmsr.c \
+ cpuid.c \
havecpuid.c
LSMSR_OBJS = $(LSMSR_SRC:%.c=%.o)
+lsmsr.c: $(LSMSR_TMP_HEADERS)
+
lsmsr: $(LSMSR_TMP_HEADERS) $(LSMSR_OBJS)
- $(CC) $(CFLAGS) -o lsmsr $(LSMSR_OBJS)
+ $(CC) $(CFLAGS) $(LDFLAGS) -o lsmsr $(LSMSR_OBJS)
+
+
--include $(LSMSR_SRC:%.c=%.P)
-X86INFO_SRC =\
- AMD/identify.c\
- AMD/bluesmoke.c\
- AMD/MSR-Athlon.c\
- AMD/MSR-K6.c\
- AMD/powernow.c\
- AMD/dumppsb.c\
- AMD/bugs.c\
-\
- Cyrix/identify.c\
-\
- Intel/identify.c\
- Intel/identify-family6.c\
- Intel/identify-family6-extended.c\
- Intel/identify-family15.c\
- Intel/info.c\
- Intel/bluesmoke.c\
- Intel/cachesize.c\
- Intel/eblcr.c\
- Intel/MSR-P4.c\
- Intel/MSR-P6.c\
- Intel/MSR-PM.c\
- Intel/microcode.c\
- Intel/topology.c\
-\
- Centaur/identify.c\
- Centaur/MSR-C3.c\
- Centaur/longhaul.c\
- Centaur/powersaver.c\
-\
- NatSemi/identify.c\
-\
- RiSE/identify.c\
-\
- SiS/identify.c\
-\
- x86info.c\
- havecpuid.c\
- cpuid.c\
- dumpregs.c\
- features.c\
- identify.c\
- rdmsr.c\
- binary.c\
- mptable.c\
- get_model_name.c\
- mtrr.c \
- connector.c\
+X86INFO_SRC = \
+ AMD/identify.c \
+ AMD/machine_check.c \
+ AMD/MSR-Athlon.c \
+ AMD/MSR-K6.c \
+ AMD/powernow.c \
+ AMD/dumppsb.c \
+ AMD/bugs.c \
+\
+ Cyrix/identify.c \
+\
+ Intel/identify.c \
+ Intel/identify-family6.c \
+ Intel/identify-family6-extended.c \
+ Intel/identify-family15.c \
+ Intel/info.c \
+ Intel/machine_check.c \
+ Intel/cachesize.c \
+ Intel/eblcr.c \
+ Intel/MSR-P4.c \
+ Intel/MSR-P6.c \
+ Intel/MSR-performance.c \
+ Intel/MSR-thermal.c \
+ Intel/MSR-IDA.c \
+ Intel/microcode.c \
+ Intel/topology.c \
+\
+ Centaur/identify.c \
+ Centaur/MSR-C3.c \
+ Centaur/longhaul.c \
+ Centaur/powersaver.c \
+\
+ NatSemi/identify.c \
+\
+ RiSE/identify.c \
+\
+ SiS/identify.c \
+\
+ x86info.c \
+ commandline.c \
+ havecpuid.c \
+ cpuid.c \
+ features.c \
+ identify.c \
+ rdmsr.c \
+ binary.c \
+ mptable.c \
+ get_model_name.c \
+ mtrr.c \
+ apic.c \
+ connector.c \
+ topology.c \
\
- bench/benchmarks.c\
+ bench/benchmarks.c \
bench/MHz.c
X86INFO_OBJS = $(X86INFO_SRC:%.c=%.o)
x86info: $(X86INFO_OBJS)
- $(CC) $(CFLAGS) -o x86info $(X86INFO_OBJS)
+ $(CC) $(CFLAGS) $(LDFLAGS) -o x86info $(X86INFO_OBJS) -lpci
--include $(X86INFO_SRC:%.c=%.P)
nodes:
@@ -101,22 +98,23 @@
test:
scripts/testnodes
-VERSION=1.24
-
release:
git repack -a -d
- git-prune-packed
- git-archive --format=tar --prefix=x86info-$(VERSION)/ HEAD | gzip -9 > x86info-$(VERSION).tgz
+ git prune-packed
+ git archive --format=tar --prefix=x86info-$(VERSION)/ HEAD | gzip -9 > x86info-$(VERSION).tgz
clean:
@find . -name "*.o" -exec rm {} \;
@find . -name "*~" -exec rm {} \;
- @find . -name "*.P" -exec rm {} \;
@rm -f x86info x86info.exe
@rm -f lsmsr $(LSMSR_TMP_HEADERS)
+ @rm -f core.*
splint:
splint +posixlib -badflag -fileextensions -type -nullassign -boolops -showcolumn -sysunrecog -fullinitblock -onlytrans -unrecog -usedef -statictrans -compdestroy -predboolint -predboolothers -D__`uname -m`__ $(X86INFO_SRC)
sparse:
sparse $(X86INFO_SRC)
+
+cscope:
+ cscope -Rb
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/NatSemi/identify.c
^
|
| @@ -9,7 +9,7 @@
#include "../x86info.h"
static char *NatSemi_nameptr;
-#define add_to_cpuname(x) NatSemi_nameptr += snprintf(NatSemi_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) NatSemi_nameptr += snprintf(NatSemi_nameptr, sizeof(x), "%s", x)
void identify_natsemi(struct cpudata *cpu)
{
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/README
^
|
| @@ -1,4 +1,4 @@
-x86info v1.24 http://www.codemonkey.org.uk/projects/x86info
+x86info v1.29 http://www.codemonkey.org.uk/projects/x86info
Dave Jones <davej@redhat.com>
Somewhere in the mists of time, there was a program by Phil Karn (KA9Q)
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/RiSE/identify.c
^
|
| @@ -9,7 +9,7 @@
#include "../x86info.h"
static char *rise_nameptr;
-#define add_to_cpuname(x) rise_nameptr += snprintf(rise_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) rise_nameptr += snprintf(rise_nameptr, sizeof(x), "%s", x)
void identify_RiSE(struct cpudata *cpu)
{
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/SiS/identify.c
^
|
| @@ -9,7 +9,7 @@
#include "../x86info.h"
static char *sis_nameptr;
-#define add_to_cpuname(x) sis_nameptr += snprintf(sis_nameptr, sizeof(x), "%s", x);
+#define add_to_cpuname(x) sis_nameptr += snprintf(sis_nameptr, sizeof(x), "%s", x)
void identify_sis(struct cpudata *cpu)
{
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/TODO
^
|
| @@ -1,43 +1,33 @@
-- Don't output same info more than once on SMP, just make a note
- that there are N identical CPUs.
-
+higher priority stuff
+---------------------
- feature flag handling code could use more cleanup.
-
+ - Would be nice to have something similar to the kernels CPU_HAS macros too.
- Make intel cache sizing use cpuid(4) where present.
-
-- Fix benchmarking
-
-- introduce hexdump option (-x) to dump register values in addition to decoding.
-
-- Identify Transmeta CPUs.
-
-- Decode mtrr registers as well as dumping them
-
-- Dump cyrix ARR registers when we pass --mtrr
-
-- --apic
- Dump APIC registers
-
-- --gcc option to output best optimisation parameters for that CPU.
-
-- Some CPUs allow the name string to be changed.
- If this has happened we die horribly. We need to store the current
- name string, perform the cpuid reset sequence, and restore the
- name string on exit.
-
- After identifying CPU we can associate more info with the CPU.
- CPU codename
- Introduction date
- number of transistors
- voltages (I/O, Core, Maximum)
- number of pipelines
+- Be able to tell the user when we have failed to identify the chip, so they can send us information!
+- Add some additional tools, rename package to 'x86utils' ?
+ - Report north bridge info (requires pci lib)
-- review code for extended natsemi support.
-- report L3 (chipset) caches (requires PCI poking)
+medium priority stuff
+---------------------
+
+- introduce hexdump option (-x) to dump register values in addition to decoding.
+- Some CPUs allow the name string to be changed.
+ If this has happened we die horribly. We need to store the current
+ name string, perform the cpuid reset sequence, and restore the
+ name string on exit.
+- Fix benchmarking
-- might be time to start thinking about XML for CPU descriptions?
-- libx86info for other apps
+low priority stuff
+------------------
+- Identify Transmeta CPUs.
+- Dump cyrix ARR registers when we pass --mtrr
+- review code for extended natsemi support.
-- Be able to tell the user when we have failed to identify the chip, so they can send us information!
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/apic.c
^
|
| @@ -0,0 +1,191 @@
+/*
+ * (C) 2011 Andre Nogueira
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * APIC register dumping.
+ * TODO : decode the registers too.
+ */
+
+#include <stdio.h>
+#include "apic.h"
+#include "x86info.h"
+
+static int fd;
+
+static int apic_msr_value(int cpu, int msr, unsigned long long *val)
+{
+ if (read_msr(cpu, msr, val) == 1)
+ return 1;
+ else
+ return 0;
+}
+
+static void dump_apic_base_msr(int cpu, int msr)
+{
+ unsigned long long val;
+ int ret;
+
+ ret = apic_msr_value(cpu, msr, &val);
+ if (ret)
+ printf("0x%016llx\n", val);
+}
+
+static int apic_is_enable(int cpu, int msr)
+{
+ unsigned long long val;
+ int ret;
+
+ ret = apic_msr_value(cpu, msr, &val);
+ if (ret)
+ ret = ((int)(val >> 11) & 0x1);
+
+ return ret;
+}
+
+static unsigned int apic_physical_address(int cpu, int msr)
+{
+ unsigned long long val;
+ unsigned int apic_phys_addr;
+ int ret;
+
+ apic_phys_addr = 0;
+
+ ret = apic_msr_value(cpu, msr, &val);
+ if (ret)
+ apic_phys_addr = ((val >> 12) << 12);
+
+ return apic_phys_addr;
+}
+
+static unsigned int * mapping_apic_registers(unsigned long addr)
+{
+ unsigned long offset;
+ void *mapped;
+
+ if ((fd = open("/dev/mem", O_RDONLY)) == -1)
+ return NULL;
+
+ offset = PAGE_OFFSET(addr);
+
+ mapped = mmap(NULL, (APIC_REGISTER_SPACE + offset), PROT_READ, MAP_PRIVATE, fd, (unsigned long) addr - offset);
+ if (mapped != MAP_FAILED)
+ return (unsigned int *) (mapped + offset);
+ else
+ return NULL;
+}
+
+static void unmapping_apic_registers(void *mapped, unsigned int size)
+{
+ if (munmap(mapped, size) == -1)
+ return;
+ if (close(fd) == -1)
+ return;
+}
+
+
+static void dump_apic(unsigned int *apic_reg_buffer, unsigned int offset)
+{
+ printf("0x%08x\n", apic_reg_buffer[ (offset * APIC_REGISTER_ALIGNED_SIZE) ]);
+}
+
+
+void dump_apics(struct cpudata *cpu)
+{
+ unsigned int *apic_reg_buffer;
+ unsigned int phys_addr;
+ int i;
+
+ /**
+ * Verify if apic feature is supported
+ **/
+ if (!(cpu->flags_edx & (X86_FEATURE_APIC)))
+ return;
+
+ /**
+ * Verify if apic is enable
+ **/
+ if (!(apic_is_enable(cpu->number, IA32_APIC_BASE_MSR)))
+ return;
+
+ phys_addr = apic_physical_address(cpu->number, IA32_APIC_BASE_MSR);
+
+ /**
+ * Mapping the apic registers
+ **/
+ apic_reg_buffer = mapping_apic_registers(phys_addr);
+ if (apic_reg_buffer == NULL)
+ return;
+
+ printf("APIC registers:\n");
+
+ printf("APIC MSR Base(0x%02x): : ", IA32_APIC_BASE_MSR);
+ dump_apic_base_msr(cpu->number, IA32_APIC_BASE_MSR);
+
+ printf("APIC Local ID : ");
+ dump_apic(apic_reg_buffer, APIC_ID);
+ printf("APIC Local Version : ");
+ dump_apic(apic_reg_buffer, APIC_VER);
+ printf("APIC Task Priority : ");
+ dump_apic(apic_reg_buffer, APIC_TPR);
+ printf("APIC Arbitration Priority : ");
+ dump_apic(apic_reg_buffer, APIC_APR);
+ printf("APIC Processor Priority : ");
+ dump_apic(apic_reg_buffer, APIC_PPR);
+ printf("APIC EOI : ");
+ dump_apic(apic_reg_buffer, APIC_EOI);
+ printf("APIC Remote Read : ");
+ dump_apic(apic_reg_buffer, APIC_RRD);
+ printf("APIC Logical Destination : ");
+ dump_apic(apic_reg_buffer, APIC_LDR);
+ printf("APIC Destination Format : ");
+ dump_apic(apic_reg_buffer, APIC_DFR);
+ printf("APIC Spurious Interrupt Vector : ");
+ dump_apic(apic_reg_buffer, APIC_SIVR);
+
+ for (i = 0 ; i < 8 ; i++) {
+ printf("APIC In-Service (ISR%d) : ", i);
+ dump_apic(apic_reg_buffer, APIC_ISR+i);
+ }
+
+ for (i = 0 ; i < 8 ; i++) {
+ printf("APIC Trigger Mode (TMR%d) : ", i);
+ dump_apic(apic_reg_buffer, APIC_TMR+i);
+ }
+
+ for (i = 0 ; i < 8 ; i++) {
+ printf("APIC Interrupt Request (IRR0%d) : ", i);
+ dump_apic(apic_reg_buffer, APIC_IRR+i);
+ }
+
+ printf("APIC Error Status : ");
+ dump_apic(apic_reg_buffer, APIC_ESR);
+ printf("APIC LVT CMCI : ");
+ dump_apic(apic_reg_buffer, APIC_LVT);
+ printf("APIC Interrupt Command (ICR0) : ");
+ dump_apic(apic_reg_buffer, APIC_ICR0);
+ printf("APIC Interrupt Command (ICR1) : ");
+ dump_apic(apic_reg_buffer, APIC_ICR1);
+ printf("APIC LVT Timer : ");
+ dump_apic(apic_reg_buffer, APIC_LVTT);
+ printf("APIC Thermal Sensor : ");
+ dump_apic(apic_reg_buffer, APIC_LVTTS);
+ printf("APIC LVT Performance Monitoring Counters: ");
+ dump_apic(apic_reg_buffer, APIC_LVTPC);
+ printf("APIC LVT LINT0 : ");
+ dump_apic(apic_reg_buffer, APIC_LVT0);
+ printf("APIC LVT LINT1 : ");
+ dump_apic(apic_reg_buffer, APIC_LVT1);
+ printf("APIC LVT Error : ");
+ dump_apic(apic_reg_buffer, APIC_LVTER);
+ printf("APIC Initial Count (for Timer) : ");
+ dump_apic(apic_reg_buffer, APIC_TICR);
+ printf("APIC Current Count (for Timer) : ");
+ dump_apic(apic_reg_buffer, APIC_TCCR);
+ printf("APIC Divide Configuration (for Timer) : ");
+ dump_apic(apic_reg_buffer, APIC_TDCR);
+
+ unmapping_apic_registers(apic_reg_buffer, APIC_REGISTER_SPACE);
+
+ printf("\n");
+}
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/apic.h
^
|
| @@ -0,0 +1,44 @@
+#ifndef _APIC_H
+#define _APIC_H
+
+#define IA32_APIC_BASE_MSR 0x1B
+
+#define APIC_REGISTER_SPACE 4096
+#define APIC_REGISTER_ALIGNED_SIZE 4
+
+#define PAGE_OFFSET(addr) ((unsigned long)(addr) & (getpagesize() - 1))
+
+enum apic_register_offset
+{
+ APIC_ID = 0x2,
+ APIC_VER = 0x3,
+ APIC_TPR = 0x8,
+ APIC_APR = 0x9,
+ APIC_PPR = 0xA,
+ APIC_EOI = 0xB,
+ APIC_RRD = 0xC,
+ APIC_LDR = 0xD,
+ APIC_DFR = 0xE,
+ APIC_SIVR = 0xF,
+ APIC_ISR = 0x10,
+ APIC_TMR = 0x18,
+ APIC_IRR = 0x20,
+ APIC_ESR = 0x28,
+ APIC_LVT = 0x2F,
+ APIC_ICR0 = 0x30,
+ APIC_ICR1 = 0x31,
+ APIC_LVTT = 0x32,
+ APIC_LVTTS = 0x33,
+ APIC_LVTPC = 0x34,
+ APIC_LVT0 = 0x35,
+ APIC_LVT1 = 0x36,
+ APIC_LVTER = 0x37,
+ APIC_TICR = 0x38,
+ APIC_TCCR = 0x39,
+ APIC_TDCR = 0x3E,
+};
+
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#endif /* _APIC_H */
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/bench/MHz.c
^
|
| @@ -15,6 +15,18 @@
#include "../x86info.h"
#include "bench.h"
+void display_MHz(struct cpudata *cpu)
+{
+ if (cpu->MHz < 1000)
+ printf("%uMHz", cpu->MHz);
+ else {
+ int a = (cpu->MHz / 1000);
+ int b = ((cpu->MHz % 1000)/100);
+ int c = (a*1000)+(b*100);
+ printf("%u.%u%uGHz", a, b, (cpu->MHz - c)/10);
+ }
+}
+
static volatile int nosignal = 0;
static void sighandler(int sig __attribute__((unused)))
@@ -28,6 +40,13 @@
unsigned int eax, ebx, ecx, edx;
unsigned long r;
+ if (cpu->number != 0) {
+ if (all_cpus == 0) {
+ cpu->MHz = firstcpu->MHz;
+ return;
+ }
+ }
+
/* Make sure we have a TSC (and hence RDTSC) */
cpuid(cpu->number, 1, &eax, &ebx, &ecx, &edx);
if ((edx & (1<<4)) == 0) {
@@ -51,7 +70,12 @@
cycles[1] = rdtsc();
- cpu->MHz = (cycles[1] - cycles[0]) / 1000000;
+ /* Check to see if rdtsc wrapped */
+ if (cycles[1] < cycles[0])
+ /* yes we did. */
+ cpu->MHz = ((-1ULL - cycles[0]) + cycles[1]) / 1000000;
+ else
+ cpu->MHz = (cycles[1] - cycles[0]) / 1000000;
if ((cpu->MHz % 50) > 15)
cpu->MHz = ((cpu->MHz / 50) * 50) + 50;
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/bench/bench.h
^
|
| @@ -1,11 +1,9 @@
static inline unsigned long long int rdtsc(void)
{
unsigned int low, high;
- unsigned long tsc;
__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
- tsc = ((unsigned long long) high << 32) | low;
- return tsc;
+ return ((unsigned long long int)high << 32) | low;
}
#define NREPS 1000
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/binary.c
^
|
| @@ -13,7 +13,7 @@
{
unsigned int i;
- for (i=0; i<n; i++, value<<=1)
+ for (i = 0; i < n; i++, value<<=1)
(void)putchar( (1<<(n-1) & value) ? '1' : '0' );
(void)putchar('\n');
}
@@ -22,10 +22,10 @@
{
int i;
- for (i=0;i<32;i++,value<<=1) {
+ for (i = 0; i < 32; i++,value<<=1) {
(void)putchar( (1<<31 & value) ? '1' : '0' );
- if (i==23 || i==15 || i==7)
+ if (i == 23 || i == 15 || i == 7)
(void)putchar(' ');
}
(void)putchar('\n');
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/commandline.c
^
|
| @@ -0,0 +1,178 @@
+/*
+ * (C) 2011 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include "x86info.h"
+
+unsigned int show_apic = 0;
+unsigned int show_bench = 0;
+unsigned int show_bios = 0;
+unsigned int show_machine_check = 0;
+unsigned int show_bugs = 0;
+unsigned int show_cacheinfo = 0;
+unsigned int show_connector = 0;
+unsigned int show_eblcr = 0;
+unsigned int show_msr = 0;
+unsigned int show_microcode = 0;
+unsigned int show_mtrr = 0;
+unsigned int show_pm = 0;
+unsigned int show_cpuid = 0;
+unsigned int show_urls = 0;
+unsigned int show_mptable = 0;
+unsigned int show_feature_flags = 0;
+unsigned int show_MHz = 0;
+unsigned int show_addr_sizes = 0;
+unsigned int all_cpus = 0;
+
+unsigned int debug = 0;
+unsigned int verbose = 0;
+unsigned int need_root = 0;
+
+
+static void usage(char *programname)
+{
+ printf("Usage: %s [<switches>]\n\
+-a, --all\n\
+ --all-cpus\n\
+ --addr\n\
+ --apic\n\
+ --bench\n\
+ --bios\n\
+ --bugs\n\
+-c, --cache\n\
+ --connector\n\
+ --debug\n\
+-f, --flags\n\
+-mce, --show-machine-check\n\
+-mhz, --mhz\n\
+ --microcode\n\
+-mp, --mptable\n\
+-m, --msr\n\
+ --mult\n\
+ --mtrr\n\
+ --pm\n\
+-r, --registers\n\
+-u, --urls\n\
+-v, --verbose\n\
+\n", programname);
+ exit (0);
+}
+
+void parse_command_line(int argc, char **argv)
+{
+ char **argp, *arg;
+
+ for (argp = argv+1; argp <= argv + argc && (arg = *argp); argp++) {
+ if ((!strcmp(arg, "-a") || !strcmp(arg, "--all"))) {
+
+ if (user_is_root) {
+ show_apic = 1;
+ show_bios = 1;
+ show_msr = 1;
+ show_microcode = 1;
+ need_root = 1;
+ show_mptable =1;
+ show_mtrr = 1;
+ show_machine_check = 1;
+ show_eblcr =1;
+ }
+ show_addr_sizes = 1;
+ show_bugs = 1;
+ show_cacheinfo = 1;
+ show_connector = 1;
+ show_feature_flags = 1;
+ show_MHz = 1;
+ show_pm = 1;
+ show_cpuid = 1;
+ show_urls = 1;
+ }
+
+ if (!strcmp(arg, "--all-cpus"))
+ all_cpus = 1;
+
+ if (!strcmp(arg, "--addr"))
+ show_addr_sizes = 1;
+
+ if (!strcmp(arg, "--apic")) {
+ need_root = 1;
+ show_apic = 1;
+ }
+
+ if (!strcmp(arg, "--bench"))
+ show_bench = 1;
+
+ if (!strcmp(arg, "--bios")) {
+ need_root = 1;
+ show_bios = 1;
+ }
+
+ if (!strcmp(arg, "--bugs"))
+ show_bugs = 1;
+
+ if ((!strcmp(arg, "-c") || !strcmp(arg, "--cache")))
+ show_cacheinfo = 1;
+
+ if (!strcmp(arg, "--connector"))
+ show_connector = 1;
+
+ if (!strcmp(arg, "--debug"))
+ debug = 1;
+
+ if ((!strcmp(arg, "-f") || !strcmp(arg, "--flags")))
+ show_feature_flags = 1;
+
+ if ((!strcmp(arg, "-m") || !strcmp(arg, "--msr"))) {
+ need_root = 1;
+ show_msr = 1;
+ }
+
+ if (!strcmp(arg, "--microcode")) {
+ need_root = 1;
+ show_microcode = 1;
+ }
+
+ if ((!strcmp(arg, "-mhz") || !strcmp(arg, "--mhz")))
+ show_MHz = 1;
+
+ if ((!strcmp(arg, "-mp") || !strcmp(arg, "--mptable"))) {
+ need_root = 1;
+ show_mptable = 1;
+ }
+
+ if (!strcmp(arg, "--mtrr")) {
+ need_root = 1;
+ show_mtrr = 1;
+ }
+
+ if (!strcmp(arg, "--mult")) {
+ need_root = 1;
+ show_eblcr = 1;
+ }
+
+ if (!strcmp(arg, "--pm"))
+ show_pm = 1;
+
+ if ((!strcmp(arg, "-r") || !strcmp(arg, "--raw-cpuid")))
+ show_cpuid = 1;
+
+ if ((!strcmp(arg, "-mce") || !strcmp(arg, "--show-machine-check"))) {
+ need_root = 1;
+ show_machine_check = 1;
+ }
+
+ if ((!strcmp(arg, "-u") || !strcmp(arg, "--urls")))
+ show_urls = 1;
+
+ if ((!strcmp(arg, "-v") || !strcmp(arg, "--verbose")))
+ verbose = 1;
+
+ if ((!strcmp(arg, "?") || !strcmp(arg, "--help")))
+ usage(argv[0]);
+ }
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/connector.c
^
|
| @@ -31,10 +31,14 @@
{CONN_SOCKET_940, "Socket 940"},
{CONN_SOCKET_S1G1, "Socket S1g1"},
{CONN_SOCKET_S1G2, "Socket S1g2"},
+ {CONN_SOCKET_S1G3, "Socket S1g3/S1g4"},
{CONN_SOCKET_F, "Socket F (1207)"},
{CONN_SOCKET_AM2, "Socket AM2"},
{CONN_SOCKET_F_R2, "Socket Fr2 (1207)"},
- {CONN_SOCKET_AM2_R2, "Socket AM2r2"},
+ {CONN_SOCKET_AM3, "Socket AM2r2/AM3"},
+ {CONN_SOCKET_G34, "Socket G34"},
+ {CONN_SOCKET_ASB2, "Socket ASB2"},
+ {CONN_SOCKET_C32, "Socket C32"},
/* Intel specific sockets */
{CONN_SOCKET_57B, "Socket 5/7 (320 Pin PGA)"},
{CONN_MOBILE_7, "Mobile Module (320 Lead TCP)"},
@@ -53,7 +57,16 @@
/* natsemi specific (Geode) */
{CONN_BGA, "BGA"}, /* */
};
-get_name(connector, enum connector, connector_strings);
+
+static const char * get_connector_name(enum connector id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(connector_strings); i++)
+ if (id == connector_strings[i].id)
+ return connector_strings[i].name;
+ return NULL;
+}
void decode_connector(enum connector type)
{
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/cpuid.c
^
|
| @@ -40,12 +40,14 @@
#endif
#endif
-static void native_cpuid(unsigned int cpunr, unsigned long long idx,
+/* returns zero on success */
+static int native_cpuid(unsigned int cpunr, unsigned long long idx,
unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
{
- cpu_set_t set;
+ cpu_set_t set, tmp_set;
unsigned int a = 0, b = 0, c = 0, d = 0;
+ int ret;
if (eax != NULL)
a = *eax;
@@ -56,11 +58,17 @@
if (edx != NULL)
d = *edx;
- if (sched_getaffinity(getpid(), sizeof(set), &set) == 0) {
- CPU_ZERO(&set);
- CPU_SET(cpunr, &set);
- sched_setaffinity(getpid(), sizeof(set), &set);
- }
+ ret = sched_getaffinity(getpid(), sizeof(set), &set);
+ if (ret)
+ return ret;
+
+ /* man CPU_SET(3): To duplicate a CPU set, use memcpy(3) */
+ memcpy(&tmp_set, &set, sizeof(cpu_set_t));
+ CPU_ZERO(&set);
+ CPU_SET(cpunr, &set);
+ ret = sched_setaffinity(getpid(), sizeof(set), &set);
+ if (ret)
+ return ret;
asm("cpuid"
: "=a" (a),
@@ -77,8 +85,16 @@
*ecx = c;
if (edx!=NULL)
*edx = d;
+
+ /* Restore initial sched affinity */
+ ret = sched_setaffinity(getpid(), sizeof(tmp_set), &tmp_set);
+ if (ret)
+ return ret;
+ return 0;
}
+static const char *NATIVE_CPUID_FAILED_MSG = "WARNING: Native cpuid failed\n";
+
#if defined(__FreeBSD__)
void cpuid(unsigned int CPU_number, unsigned long long idx,
unsigned int *eax,
@@ -93,7 +109,8 @@
cpu_cpuid_args_t args;
if (nodriver == 1) {
- native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
+ if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx))
+ printf("%s", NATIVE_CPUID_FAILED_MSG);
return;
}
@@ -117,10 +134,11 @@
} else {
/* Something went wrong, just do UP and hope for the best. */
nodriver = 1;
- if (!silent && nrCPUs != 1)
+ if (nrCPUs != 1)
perror(cpuname);
- used_UP = 1;
- native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
+ if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx))
+ printf("%s", NATIVE_CPUID_FAILED_MSG);
+
return;
}
}
@@ -141,6 +159,7 @@
static int nodriver=0;
char cpuname[20];
unsigned char buffer[CPUID_CHUNK_SIZE];
+ unsigned int *ptr = (unsigned int *)buffer;
int fh;
if (eax != NULL) {
@@ -150,7 +169,8 @@
}
if (nodriver == 1) {
- native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
+ if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx))
+ printf("%s", NATIVE_CPUID_FAILED_MSG);
return;
}
@@ -171,10 +191,10 @@
perror(cpuname);
exit(EXIT_FAILURE);
}
- if (eax!=0) *eax = (*(unsigned *)(buffer ));
- if (ebx!=0) *ebx = (*(unsigned *)(buffer+ 4));
- if (ecx!=0) *ecx = (*(unsigned *)(buffer+ 8));
- if (edx!=0) *edx = (*(unsigned *)(buffer+12));
+ if (eax!=0) *eax = *ptr;
+ if (ebx!=0) *ebx = *(++ptr);
+ if (ecx!=0) *ecx = *(++ptr);
+ if (edx!=0) *edx = *(++ptr);
if (close(fh) == -1) {
perror("close");
exit(EXIT_FAILURE);
@@ -182,8 +202,8 @@
} else {
/* Something went wrong, just do UP and hope for the best. */
nodriver = 1;
- used_UP = 1;
- native_cpuid(CPU_number, idx, eax,ebx,ecx,edx);
+ if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx))
+ printf("%s", NATIVE_CPUID_FAILED_MSG);
return;
}
}
@@ -195,3 +215,35 @@
{
cpuid(CPU_number, 4 | (idx << 32), eax, ebx, ecx, edx);
}
+
+/* Some CPUID calls want 'count' to be placed in ecx */
+void cpuid_count(unsigned int CPU_number, unsigned int op, int count,
+ unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ *ecx = count;
+ cpuid(CPU_number, op, eax, ebx, ecx, edx);
+}
+
+unsigned int cpuid_ebx(unsigned int CPU_number, unsigned int op)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ cpuid(CPU_number, op, &eax, &ebx, &ecx, &edx);
+
+ return ebx;
+}
+
+
+void dump_raw_cpuid(int cpunum, unsigned int begin, unsigned int end)
+{
+ unsigned int i;
+ unsigned int eax, ebx, ecx, edx;
+
+ /* Dump all the CPUID results in raw hex */
+ for (i = begin; i <= end; i++) {
+ cpuid(cpunum, i, &eax, &ebx, &ecx, &edx);
+ printf("eax in: 0x%08x, eax = %08x ebx = %08x ecx = %08x edx = %08x\n", i, eax, ebx, ecx, edx);
+ }
+ printf("\n");
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/features.c
^
|
| @@ -1,5 +1,5 @@
/*
- * (C) 2001-2006 Dave Jones.
+ * (C) 2001-2010 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
@@ -7,18 +7,31 @@
*/
#include <stdio.h>
+#include <signal.h>
+#include <setjmp.h>
#include "x86info.h"
-static void flag_decode(unsigned long reg, const char *flags[])
+static void flag_decode(unsigned long reg, const char * reg_desc, const char *flags[], const char *flags_desc[])
{
unsigned int i;
- for (i=0; i<32; i++) {
+ for (i = 0; i < 32; i++) {
if (reg & (1<<i)) {
- if (flags[i])
- printf(" %s", flags[i]);
- else
- printf(" [%u]", i);
+ if (!verbose) {
+ if (flags[i])
+ printf(" %s", flags[i]);
+ else
+ printf(" [%s:%u]", reg_desc, i);
+ } else {
+ if (flags[i])
+ printf(" %-8s", flags[i]);
+ else
+ printf(" [%s:%u] ", reg_desc, i);
+ if (flags_desc)
+ printf("\t%s\n", flags_desc[i]);
+ else
+ printf("\n");
+ }
}
}
}
@@ -38,10 +51,108 @@
}
}
-void show_feature_flags(struct cpudata *cpu)
+void show_extra_intel_flags(struct cpudata *cpu)
+{
+ unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0;
+ /* CPUID 0x00000006 EAX flags */
+ const char *intel_cpuid_06_eax_flags[] = {
+ "dts", "ida", "arat", NULL, "pln", "ecmd", "ptm", NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+ };
+ const char *intel_cpuid_06_eax_flags_desc[] = {
+ "Digital temperature sensor supported", // 0
+ "Intel Dynamic Acceleration Technology (Turbo Boost)", // 1
+ "Always Running APIC Timer", // 2
+ NULL, // 3
+ "Power limit notification controls", // 4
+ "Clock modulation duty cycle extension", // 5
+ "Package thermal management", // 6
+ NULL, // 7
+ NULL, // 8
+ NULL, // 9
+ NULL, // 10
+ NULL, // 11
+ NULL, // 12
+ NULL, // 13
+ NULL, // 14
+ NULL, // 15
+ NULL, // 16
+ NULL, // 17
+ NULL, // 18
+ NULL, // 19
+ NULL, // 20
+ NULL, // 21
+ NULL, // 22
+ NULL, // 23
+ NULL, // 24
+ NULL, // 25
+ NULL, // 26
+ NULL, // 27
+ NULL, // 28
+ NULL, // 29
+ NULL, // 30
+ NULL // 31
+ };
+
+ /* CPUID 0x80000007 EDX flags */
+ const char *intel_cpuid_80000007_edx_flags[] = {
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "nonstop_tsc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+ };
+ const char *intel_cpuid_80000007_edx_flags_desc[] = {
+ NULL, // 0
+ NULL, // 1
+ NULL, // 2
+ NULL, // 3
+ NULL, // 4
+ NULL, // 5
+ NULL, // 6
+ NULL, // 7
+ "Invariant/nonstop/constant TSC", // 8
+ NULL, // 9
+ NULL, // 10
+ NULL, // 11
+ NULL, // 12
+ NULL, // 13
+ NULL, // 14
+ NULL, // 15
+ NULL, // 16
+ NULL, // 17
+ NULL, // 18
+ NULL, // 19
+ NULL, // 20
+ NULL, // 21
+ NULL, // 22
+ NULL, // 23
+ NULL, // 24
+ NULL, // 25
+ NULL, // 26
+ NULL, // 27
+ NULL, // 28
+ NULL, // 29
+ NULL, // 30
+ NULL // 31
+ };
+
+ // Intel CPUID 0x06
+ if (cpu->cpuid_level >= 0x06) {
+ cpuid(cpu->number, 0x06, &eax, &ebx, &ecx, &edx);
+ flag_decode(eax, "6:eax", intel_cpuid_06_eax_flags, intel_cpuid_06_eax_flags_desc);
+ }
+ // Intel CPUID 0x80000007
+ if (cpu->maxei >= 0x80000007) {
+ cpuid(cpu->number, 0x80000007, &eax, &ebx, &ecx, &edx);
+ flag_decode(edx, "80000007:edx", intel_cpuid_80000007_edx_flags, intel_cpuid_80000007_edx_flags_desc);
+ }
+}
+
+static void decode_feature_flags(struct cpudata *cpu)
{
unsigned int eax, ebx, ecx, edx;
- unsigned int i;
/* CPUID 0x00000001 EDX flags */
const char *generic_cap_flags[] = {
@@ -51,52 +162,120 @@
"fxsr", "sse", "sse2", "ss", "ht", "tm", NULL, "pbe"
};
const char *generic_cap_flags_desc[] = {
- "Onboard FPU",
- "Virtual Mode Extensions",
- "Debugging Extensions",
- "Page Size Extensions",
- "Time Stamp Counter",
- "Model-Specific Registers",
- "Physical Address Extensions",
- "Machine Check Architecture",
- "CMPXCHG8 instruction",
- "Onboard APIC",
- NULL,
- "SYSENTER/SYSEXIT",
- "Memory Type Range Registers",
- "Page Global Enable",
- "Machine Check Architecture",
- "CMOV instruction",
- "Page Attribute Table",
- "36-bit PSEs",
- "Processor serial number", /* reserved on AMD */
- "CLFLUSH instruction",
- NULL,
- "Debug Trace Store", /* reserved on AMD */
- "ACPI via MSR", /* reserved on AMD */
- "MMX support",
- "FXSAVE and FXRESTORE instructions",
- "SSE support",
- "SSE2 support",
- "CPU self snoop", /* reserved on AMD */
- "Hyper-Threading",
- "Thermal Monitor", /* reserved on AMD */
- NULL,
- "Pending Break Enable" /* reserved on AMD */
+ "Onboard FPU", // 0
+ "Virtual Mode Extensions", // 1
+ "Debugging Extensions", // 2
+ "Page Size Extensions", // 3
+ "Time Stamp Counter", // 4
+ "Model-Specific Registers", // 5
+ "Physical Address Extensions", // 6
+ "Machine Check Exception", // 7
+ "CMPXCHG8 instruction", // 8
+ "Onboard APIC", // 9
+ NULL, // 10
+ "SYSENTER/SYSEXIT instructions", // 11
+ "Memory Type Range Registers", // 12
+ "Page Global Enable", // 13
+ "Machine Check Architecture", // 14
+ "CMOV instruction", // 15
+ "Page Attribute Table", // 16
+ "36-bit PSEs", // 17
+ "Processor serial number", /* reserved on AMD */ // 18
+ "CLFLUSH instruction", // 19
+ NULL, // 20
+ "Debug Trace Store", /* reserved on AMD */ // 21
+ "ACPI via MSR", /* reserved on AMD */ // 22
+ "MMX support", // 23
+ "FXSAVE and FXRSTOR instructions", // 24
+ "SSE support", // 25
+ "SSE2 support", // 26
+ "CPU self snoop", /* reserved on AMD */ // 27
+ "Hyper-Threading", // 28
+ "Thermal Monitor", /* reserved on AMD */ // 29
+ NULL, // 30
+ "Pending Break Enable" /* reserved on AMD */ // 31
};
/* CPUID 0x00000001 ECX flags */
const char *intel_cap_generic_ecx_flags[] = {
- "sse3", NULL, NULL, "monitor", "ds-cpl", "vmx", NULL, "est",
- "tm2", "ssse3", "cntx-id", NULL, NULL, "cx16", "xTPR", NULL,
- NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+ "sse3", "pclmuldq", "dtes64", "monitor", "ds-cpl", "vmx", "smx", "est",
+ "tm2", "ssse3", "cid", NULL, "fma", "cx16", "xTPR", "pdcm",
+ NULL, "pcid", "dca", "sse4_1", "sse4_2", "x2apic", "movbe", "popcnt",
+ "tsc-deadline", "aes", "xsave", "osxsave", "avx", NULL, NULL, NULL
+ };
+ const char *intel_cap_generic_ecx_flags_desc[] = {
+ "Streaming SIMD Extensions 3", // 0
+ "PCLMULDQ Instruction", // 1
+ "64-Bit Debug Store", // 2
+ "MONITOR/MWAIT", // 3
+ "CPL Qualified Debug Store", // 4
+ "Virtual Machine Extensions", // 5
+ "Safer Mode Extensions", // 6
+ "Enhanced Intel SpeedStep Technology", // 7
+ "Thermal Monitor 2", // 8
+ "Supplemental Streaming SIMD Extensions 3", // 9
+ "L1 Context ID", // 10
+ NULL, // 11
+ "Fused Multiply Add", // 12
+ "CMPXCHG16B", // 13
+ "xTPR Update Control", // 14
+ "Perfmon and Debug Capability", // 15
+ NULL, // 16
+ "Process-context identifiers", // 17
+ "Direct Cache Access", // 18
+ "Streaming SIMD Extensions 4.1", // 19
+ "Streaming SIMD Extensions 4.2", // 20
+ "Extended xAPIC Support", // 21
+ "MOVBE Instruction", // 22
+ "POPCNT Instruction", // 23
+ "TSC Deadline support", // 24
+ "AES Instruction", // 25
+ "XSAVE/XSTOR States", // 26
+ "OS-Enabled Extended State Management", // 27
+ "AVX instruction extensions", // 28
+ NULL, // 29
+ NULL, // 30
+ NULL // 31
};
/* CPUID 0x80000001 EDX flags */
const char *intel_cap_extended_edx_flags[] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, "SYSCALL", NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, "xd", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, "em64t", NULL, NULL,
+ NULL, NULL, "pdpe1gb", "rdtscp", NULL, "em64t", NULL, NULL,
+ };
+ const char *intel_cap_extended_edx_flags_desc[] = {
+ NULL, // 0
+ NULL, // 1
+ NULL, // 2
+ NULL, // 3
+ NULL, // 4
+ NULL, // 5
+ NULL, // 6
+ NULL, // 7
+ NULL, // 8
+ NULL, // 9
+ NULL, // 10
+ "SYSCALL/SYSRET instructions", // 11
+ NULL, // 12
+ NULL, // 13
+ NULL, // 14
+ NULL, // 15
+ NULL, // 16
+ NULL, // 17
+ NULL, // 18
+ NULL, // 19
+ "Execution Disable Bit", // 20
+ NULL, // 21
+ NULL, // 22
+ NULL, // 23
+ NULL, // 24
+ NULL, // 25
+ "1-GByte pages", // 26
+ "RDTSCP and IA32_TSC_AUX", // 27
+ NULL, // 28
+ "Intel 64 Instruction Set Architecture", // 29
+ NULL, // 30
+ NULL // 31
};
/* CPUID 0x80000001 ECX flags */
const char *intel_cap_extended_ecx_flags[] = {
@@ -105,12 +284,79 @@
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
+ const char *intel_cap_extended_ecx_flags_desc[] = {
+ "LAHF/SAHF available in 64-bit mode", // 0
+ NULL, // 1
+ NULL, // 2
+ NULL, // 3
+ NULL, // 4
+ NULL, // 5
+ NULL, // 6
+ NULL, // 7
+ NULL, // 8
+ NULL, // 9
+ NULL, // 10
+ NULL, // 11
+ NULL, // 12
+ NULL, // 13
+ NULL, // 14
+ NULL, // 15
+ NULL, // 16
+ NULL, // 17
+ NULL, // 18
+ NULL, // 19
+ NULL, // 19
+ NULL, // 20
+ NULL, // 22
+ NULL, // 23
+ NULL, // 24
+ NULL, // 25
+ NULL, // 26
+ NULL, // 27
+ NULL, // 28
+ NULL, // 29
+ NULL, // 30
+ NULL // 31
+ };
const char *amd_cap_generic_ecx_flags[] = {
- "sse3", NULL, NULL, "mwait", NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, "cmpxchg16b", NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, "popcnt",
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+ "sse3", "pclmulqdq", NULL, "mwait", NULL, NULL, NULL, NULL,
+ NULL, "ssse3", NULL, NULL, "fma", "cmpxchg16b", NULL, NULL,
+ NULL, NULL, NULL, "sse4_1", "sse4_2", NULL, NULL, "popcnt",
+ NULL, "aes", "xsave", "osxsave", "avx", "f16c", NULL, NULL
+ };
+ const char *amd_cap_generic_ecx_flags_desc[] = {
+ "Streaming SIMD Extensions 3", // 0
+ NULL, // 1
+ NULL, // 2
+ "MONITOR/MWAIT instructions", // 3
+ NULL, // 4
+ NULL, // 5
+ NULL, // 6
+ NULL, // 7
+ NULL, // 8
+ "Supplemental Streaming SIMD Extensions 3", // 9
+ NULL, // 10
+ NULL, // 11
+ NULL, // 12
+ "CMPXCHG16B instruction", // 13
+ NULL, // 14
+ NULL, // 15
+ NULL, // 16
+ NULL, // 17
+ NULL, // 18
+ "Streaming SIMD Extensions 4.1", // 19
+ NULL, // 20
+ NULL, // 22
+ "POPCNT instruction", // 23
+ NULL, // 24
+ NULL, // 25
+ NULL, // 26
+ NULL, // 27
+ NULL, // 28
+ NULL, // 29
+ NULL, // 30
+ NULL // 31
};
const char *amd_cap_extended_edx_flags[] = {
"fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
@@ -123,8 +369,10 @@
const char *amd_cap_extended_ecx_flags[] = {
"lahf/sahf", "CmpLegacy", "svm", "ExtApicSpace",
"LockMovCr0", "abm", "sse4a", "misalignsse",
- "3dnowPref", "osvw", "ibs", NULL, "skinit", "wdt", NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "3dnowPref", "osvw", "ibs", "xop",
+ "skinit", "wdt", NULL, "lwp",
+ "fma4", NULL, NULL, "NodeId",
+ NULL, "tbm", "TopoExt", NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
};
@@ -149,49 +397,37 @@
};
printf("Feature flags:\n");
- for (i=0; i<32; i++) {
- if (cpu->flags_edx & (1 << i)) {
- if (!(generic_cap_flags_desc[i]))
- printf(" [%u]", i);
- if (verbose)
- printf("\t%s\n", generic_cap_flags_desc[i]);
- else
- printf(" %s", generic_cap_flags[i]);
- }
- }
+ flag_decode(cpu->flags_edx, "1:edx", generic_cap_flags, generic_cap_flags_desc);
/* Vendor specific extensions. */
switch (cpu->vendor) {
case VENDOR_AMD:
- for (i=0; i<32; i++) {
- if (cpu->flags_ecx & (1 << i) && amd_cap_generic_ecx_flags[i])
- printf(" %s", amd_cap_generic_ecx_flags[i]);
- }
+ flag_decode(cpu->flags_ecx, "1:ecx", amd_cap_generic_ecx_flags, amd_cap_generic_ecx_flags_desc);
printf("\n");
if (cpu->maxei < 0x80000001)
break;
printf("Extended feature flags:\n");
- flag_decode(cpu->eflags_edx, amd_cap_extended_edx_flags);
- flag_decode(cpu->eflags_ecx, amd_cap_extended_ecx_flags);
+ flag_decode(cpu->eflags_edx, "80000001:edx", amd_cap_extended_edx_flags, NULL);
+ flag_decode(cpu->eflags_ecx, "80000001:ecx", amd_cap_extended_ecx_flags, NULL);
printf("\n");
break;
case VENDOR_CENTAUR:
printf("\n");
printf("Extended feature flags:\n");
- flag_decode(cpu->flags_ecx, centaur_cap_extended_ecx_flags);
+ flag_decode(cpu->flags_ecx, "1:ecx", centaur_cap_extended_ecx_flags, NULL);
cpuid(cpu->number, 0xc0000000, &eax, &ebx, &ecx, &edx);
if (eax >=0xc0000001) {
cpuid(cpu->number, 0xc0000001, &eax, &ebx, &ecx, &edx);
cpu->flags_edx = edx;
- flag_decode(cpu->flags_edx, centaur_cap_extended_edx_flags);
+ flag_decode(cpu->flags_edx, "1:edx", centaur_cap_extended_edx_flags, NULL);
}
break;
case VENDOR_TRANSMETA:
printf("\n");
printf("Extended feature flags:\n");
- flag_decode(cpu->flags_ecx, transmeta_cap_flags);
+ flag_decode(cpu->flags_ecx, "1:ecx", transmeta_cap_flags, NULL);
break;
case VENDOR_CYRIX:
@@ -199,14 +435,14 @@
break;
case VENDOR_INTEL:
+ flag_decode(cpu->flags_ecx, "1:ecx", intel_cap_generic_ecx_flags, intel_cap_generic_ecx_flags_desc);
printf("\n");
- printf("Extended feature flags:\n");
- flag_decode(cpu->flags_ecx, intel_cap_generic_ecx_flags);
if (cpu->maxei < 0x80000001)
break;
- printf("\n");
- flag_decode(cpu->eflags_edx, intel_cap_extended_edx_flags);
- flag_decode(cpu->eflags_ecx, intel_cap_extended_ecx_flags);
+ printf("Extended feature flags:\n");
+ flag_decode(cpu->eflags_edx, "80000001:edx", intel_cap_extended_edx_flags, intel_cap_extended_edx_flags_desc);
+ flag_decode(cpu->eflags_ecx, "80000001:ecx", intel_cap_extended_ecx_flags, intel_cap_extended_ecx_flags_desc);
+ show_extra_intel_flags(cpu);
break;
default:
@@ -216,3 +452,31 @@
printf("\n");
}
+
+static sigjmp_buf out;
+
+static void sigill(__attribute__((__unused__))int sig)
+{
+ siglongjmp(out, 1);
+}
+
+static void test_longnop(void)
+{
+ int died;
+
+ signal(SIGILL, sigill);
+
+ died = sigsetjmp(out, 1);
+
+ if (!died)
+ asm volatile("nopl 0(%eax)");
+
+ printf("Long NOPs supported: %s\n", died ? "no" : "yes");
+}
+
+void display_feature_flags(struct cpudata *cpu)
+{
+ decode_feature_flags(cpu);
+ test_longnop();
+ printf("\n");
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/get_model_name.c
^
|
| @@ -42,7 +42,7 @@
if (strstr(cp, "unknown") != NULL) {
unsigned int vendor;
cpuid(cpu->number, 0, NULL, &vendor, NULL, NULL);
- if (vendor == 0x68747541 && cpu->maxi >= 1 && cpu->maxei >= 0x80000001) { /* AMD defined flags */
+ if (vendor == 0x68747541 && cpu->cpuid_level >= 1 && cpu->maxei >= 0x80000001) { /* AMD defined flags */
unsigned int bid, ebid;
cpuid(cpu->number, 0x00000001, NULL, &bid, NULL, NULL);
bid &= 0xff;
@@ -125,5 +125,5 @@
}
}
- printf("Processor name string: %s\n", cp);
+ printf("Processor name string (BIOS programmed): %s\n", cp);
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/identify.c
^
|
| @@ -9,13 +9,13 @@
void get_cpu_info_basics(struct cpudata *cpu)
{
- unsigned int maxi, maxei, vendor;
+ unsigned int maxi, maxei, vendor, address_bits;
unsigned int eax;
cpuid(cpu->number, 0, &maxi, &vendor, NULL, NULL);
maxi &= 0xffff; /* The high-order word is non-zero on some Cyrix CPUs */
- cpu->maxi = maxi;
- if (cpu->maxi < 1)
+ cpu->cpuid_level = maxi;
+ if (maxi < 1)
return;
/* Everything that supports cpuid supports these. */
@@ -30,6 +30,10 @@
cpuid(cpu->number, 0xC0000000, &maxei, NULL, NULL, NULL);
cpu->maxei2 = maxei;
+ cpuid(cpu->number, 0x80000008,&address_bits, NULL, NULL, NULL);
+ cpu->phyaddr_bits = address_bits & 0xFF;
+ cpu->viraddr_bits = (address_bits >> 8) & 0xFF;
+
switch (vendor) {
case 0x756e6547:
cpu->vendor = VENDOR_INTEL;
@@ -91,15 +95,17 @@
void show_info(struct cpudata *cpu)
{
- if (silent)
- return;
-
- printf("EFamily: %u EModel: %u Family: %u Model: %u Stepping: %u\n",
- cpu->efamily, cpu->emodel, cpu->family,
- model(cpu), cpu->stepping);
- printf("CPU Model: %s\n", cpu->name);
-
+ if ((cpu->efamily != 0) || (cpu->emodel != 0))
+ printf("Extended Family: %u Extended Model: %u ",
+ cpu->efamily, cpu->emodel);
+ printf("Family: %u Model: %u Stepping: %u\n",
+ cpu->family, model(cpu), cpu->stepping);
+ if (cpu->vendor == VENDOR_INTEL)
+ display_basic_Intel_info(cpu);
+ printf("CPU Model (x86info's best guess): %s\n", cpu->name);
get_model_name(cpu);
+ printf("\n");
+
switch (cpu->vendor) {
case VENDOR_AMD:
@@ -115,7 +121,7 @@
break;
case VENDOR_INTEL:
- display_Intel_info(cpu);
+ display_extended_Intel_info(cpu);
break;
default:
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/lsmsr.c
^
|
| @@ -25,10 +25,10 @@
#include <getopt.h>
#include "msr.h"
-#include "cpuid.h"
#include "x86info.h"
#include "AMD/k8.h"
#include "AMD/fam10h.h"
+#include "AMD/fam11h.h"
#include "generic_msr.h"
/* Todos:
@@ -38,7 +38,7 @@
* - add support for generic MSRs for non-Intel/AMD CPUs
*/
-#define VERSION "0.815"
+#define VERSION "0.816"
struct {
int fd;
@@ -58,7 +58,6 @@
.reg = -1,
};
-int used_UP = 0;
/* getopt_long stuff */
static struct option lopts[] = {
@@ -177,14 +176,16 @@
int ret = 0;
t = strlen(name);
- if (t<n)
+ if (t < n)
n = t;
g.show_all = 1;
for (i = 0; g.msr_table[i].name; i++) {
t = strlen(g.msr_table[i].name);
- if (n<t)
+ if (n < t)
t = n;
+ if (t < n)
+ continue;
if (strncmp(name, g.msr_table[i].name, t) == 0)
if (_show_msr(&(g.msr_table[i]))) {
ret = 1;
@@ -280,6 +281,9 @@
case 0x10:
g.msr_table = fam10h_spec;
break;
+ case 0x11:
+ g.msr_table = fam11h_spec;
+ break;
default:
g.msr_table = generic_msr_spec;
}
@@ -360,7 +364,7 @@
if ((argc - optind) != 1)
usage();
if (strlen(argv[optind]) >= OPT_MAX) {
- fprintf(stderr,"error: invlalid command line\n");
+ fprintf(stderr,"error: invalid command line\n");
goto out;
}
g.msr_search = argv[optind];
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/mptable.c
^
|
| @@ -72,7 +72,7 @@
static int nbus;
static int napic;
static int nintr;
-static int verbose_mp;
+static int silent;
typedef struct TABLE_ENTRY {
u8 type;
@@ -176,13 +176,13 @@
/* count it */
++ncpu;
- if (verbose_mp) {
+ if (!silent) {
printf("#\t%2d", (int) entry.apicID);
printf("\t 0x%2x", (unsigned int) entry.apicVersion);
printf("\t %s, %s",
- (entry.cpuFlags & PROCENTRY_FLAG_BP) ? "BSP" : "AP",
- (entry.cpuFlags & PROCENTRY_FLAG_EN) ? "usable" : "unusable");
+ (entry.cpuFlags & PROCENTRY_FLAG_BP) ? "BSP" : "AP",
+ (entry.cpuFlags & PROCENTRY_FLAG_EN) ? "usable" : "unusable");
t = (int) entry.cpuSignature;
family = (t >> 8) & 0xf;
@@ -191,6 +191,7 @@
family += (t >> 20) & 0xff;
model += (t >> 12) & 0xf0;
}
+
printf("\t %d\t %d\t %d", family, model, t & 0xf);
printf("\t 0x%04x\n", entry.featureFlags);
}
@@ -202,7 +203,7 @@
vm_offset_t paddr;
mpcth_t cth;
int x;
- int totalSize, t;
+ int totalSize;
int count, c;
if (pap == 0) {
@@ -230,14 +231,14 @@
nintr = 0;
/* process all the CPUs */
- if (verbose_mp)
+ if (!silent)
printf("MP Table:\n#\tAPIC ID\tVersion\tState\t\tFamily\tModel\tStep\tFlags\n");
- for (t = totalSize, c = count; c; c--) {
+ for (c = count; c; c--) {
if (readType() == 0)
processorEntry();
totalSize -= basetableEntryTypes[ 0 ].length;
}
- if (verbose_mp)
+ if (!silent)
printf("\n");
return SMP_YES;
@@ -357,6 +358,8 @@
vm_offset_t paddr;
mpfps_t mpfps;
+ silent = 1;
+
/* open physical memory for access to MP structures */
if ((pfd = open("/dev/mem", O_RDONLY)) < 0) {
fprintf(stderr, "enumerate_cpus(): /dev/mem: %s\n", strerror(errno));
@@ -379,40 +382,28 @@
return 1;
}
-int issmp(int verb)
+void display_mptable()
{
vm_offset_t paddr;
mpfps_t mpfps;
- verbose_mp=verb;
+ silent = 0;
+
/* open physical memory for access to MP structures */
if ((pfd = open("/dev/mem", O_RDONLY)) < 0) {
- fprintf(stderr, "issmp(): /dev/mem: %s\n", strerror(errno));
- return -1;
+ fprintf(stderr, "%s(): /dev/mem: %s\n", __func__, strerror(errno));
+ return;
}
/* probe for MP structures */
if (apic_probe(&paddr) <= 0)
- return SMP_NO;
+ return;
/* read in mpfps structure*/
seekEntry(paddr);
readEntry(&mpfps, sizeof(mpfps_t));
- /* check whether an MP config table exists */
+ /* parse an MP config table if it exists */
if (!mpfps.mpfb1)
- return MPConfigTableHeader(mpfps.pap);
-
- return SMP_NO;
-}
-
-#ifdef STANDALONE
-int main()
-{
- int numcpu, smp;
- numcpu = enumerate_cpus();
- smp = issmp(1);
- printf("SMP: %d\nCPU: %d\n", smp, numcpu);
- return 0;
+ (void) MPConfigTableHeader(mpfps.pap);
}
-#endif
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/mptable.h
^
|
| @@ -4,6 +4,6 @@
#define SMP_NO 0
#define SMP_YES 1
-int issmp(int verbose);
+void display_mptable();
#endif
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/mtrr.c
^
|
| @@ -8,8 +8,65 @@
*/
#include <stdio.h>
+#include <asm/mtrr.h>
#include "x86info.h"
+#define IA32_MTRRCAP_SMRR 0x800
+#define IA32_MTRRCAP_WC 0x400
+#define IA32_MTRRCAP_FIX 0x100
+#define IA32_MTRRCAP_VCNT 0xFF
+
+#define IA32_MTRR_DEFTYPE_E 0x800
+#define IA32_MTRR_DEFTYPE_FE 0x400
+#define IA32_MTRR_DEFTYPE_TYPE 0xFF
+
+#define IA32_PHYBASE_TYPE 0XFF
+#define IA32_PHYMASK_VALID 0X800
+
+static unsigned int max_phy_addr = 0;
+
+static char * mtrr_types[MTRR_NUM_TYPES] =
+{
+ "uncacheable",
+ "write-combining",
+ "?",
+ "?",
+ "write-through",
+ "write-protect",
+ "write-back",
+};
+
+static void decode_address(unsigned long long val)
+{
+ switch (max_phy_addr) {
+ case 40:
+ printf("0x%07x ", (unsigned int) ((val >> 12) & 0xFFFFFFF));
+ break;
+ case 36:
+ default:
+ printf("0x%06x ", (unsigned int) ((val >> 12) & 0xFFFFFF));
+ break;
+ }
+}
+
+static void set_max_phy_addr(struct cpudata *cpu)
+{
+ unsigned int value;
+
+ if (!max_phy_addr) {
+ cpuid(cpu->number, 0x80000008,&value, NULL, NULL, NULL);
+ max_phy_addr = (value & 0xFF);
+ }
+}
+
+static int mtrr_value(int cpu, int msr, unsigned long long * val)
+{
+ if (read_msr(cpu, msr, val) == 1)
+ return 1;
+ else
+ return 0;
+}
+
static void dump_mtrr(int cpu, int msr)
{
unsigned long long val=0;
@@ -18,23 +75,97 @@
printf("0x%016llx\n", val);
}
+static void decode_mtrrcap(int cpu, int msr)
+{
+ unsigned long long val;
+ int ret;
+
+ ret = mtrr_value(cpu,msr,&val);
+ if (ret) {
+ printf("0x%016llx ", val);
+ printf("(smrr flag: 0x%01x, ",(unsigned int) (val & IA32_MTRRCAP_SMRR) >> 11 );
+ printf("wc flag: 0x%01x, ",(unsigned int) (val&IA32_MTRRCAP_WC) >> 10);
+ printf("fix flag: 0x%01x, ",(unsigned int) (val&IA32_MTRRCAP_FIX) >> 8);
+ printf("vcnt field: 0x%02x (%d))\n",(unsigned int) (val&IA32_MTRRCAP_VCNT) , (int) (val&IA32_MTRRCAP_VCNT));
+ }
+}
+
+static void decode_mtrr_deftype(int cpu, int msr)
+{
+ unsigned long long val;
+ int ret;
+
+ ret = mtrr_value(cpu,msr,&val);
+ if (ret) {
+ printf("0x%016llx ", val);
+ printf("(fixed-range flag: 0x%01x, ",(unsigned int) (val&IA32_MTRR_DEFTYPE_FE) >> 10);
+ printf("mtrr flag: 0x%01x, ",(unsigned int) (val&IA32_MTRR_DEFTYPE_E) >> 11);
+ printf("type field: 0x%02x (%s))\n", (unsigned int) (val&IA32_MTRR_DEFTYPE_TYPE) >> 8,
+ mtrr_types[((val&IA32_MTRR_DEFTYPE_TYPE) >> 8)]);
+ }
+}
+
+static void decode_mtrr_physbase(int cpu, int msr)
+{
+ unsigned long long val;
+ int ret;
+
+ ret = mtrr_value(cpu,msr,&val);
+ if (ret) {
+ printf("0x%016llx ", val);
+
+ printf("(physbase field:");
+ decode_address(val);
+
+ printf("type field: 0x%02x (%s))\n",(unsigned int) (val&IA32_PHYBASE_TYPE),
+ mtrr_types[((val&IA32_PHYBASE_TYPE))]);
+ }
+}
+
+static void decode_mtrr_physmask(int cpu, int msr)
+{
+ unsigned long long val;
+ int ret;
+
+ ret = mtrr_value(cpu,msr,&val);
+ if (ret) {
+ printf("0x%016llx ", val);
+
+ printf("(physmask field:");
+ decode_address(val);
+
+ printf("valid flag: %d)\n",(int) (val&IA32_PHYMASK_VALID)>>11);
+ }
+}
+
+
void dump_mtrrs(struct cpudata *cpu)
{
+ unsigned long long val = 0;
unsigned int i;
if (!(cpu->flags_edx & (X86_FEATURE_MTRR)))
return;
+ /*
+ * If MTRR registers are not accessible like in some
+ * virtualization systems then return
+ */
+ if (!read_msr(cpu->number, 0xfe, &val))
+ return;
+
printf("MTRR registers:\n");
printf("MTRRcap (0xfe): ");
- dump_mtrr(cpu->number, 0xfe);
+ decode_mtrrcap(cpu->number, 0xfe);
+
+ set_max_phy_addr(cpu);
- for (i=0; i<16; i+=2) {
+ for (i = 0; i < 16; i+=2) {
printf("MTRRphysBase%u (0x%x): ", i/2, (unsigned int) 0x200+i);
- dump_mtrr(cpu->number, 0x200+i);
+ decode_mtrr_physbase(cpu->number, 0x200+i);
printf("MTRRphysMask%u (0x%x): ", i/2, (unsigned int) 0x201+i);
- dump_mtrr(cpu->number, 0x201+i);
+ decode_mtrr_physmask(cpu->number, 0x201+i);
}
printf("MTRRfix64K_00000 (0x250): ");
@@ -60,7 +191,7 @@
dump_mtrr (cpu->number, 0x26f);
printf("MTRRdefType (0x2ff): ");
- dump_mtrr (cpu->number, 0x2ff);
+ decode_mtrr_deftype(cpu->number, 0x2ff);
- printf("\n\n");
+ printf("\n");
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/rdmsr.c
^
|
| @@ -8,6 +8,7 @@
* Routines for reading MSRs.
*/
+#define _LARGEFILE64_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
@@ -39,8 +40,7 @@
fh = open(cpuname, O_RDONLY);
if (fh==-1) {
- if (!silent)
- perror(cpuname);
+ perror(cpuname);
nodriver=1;
return 0;
}
@@ -73,6 +73,7 @@
unsigned long lo, hi;
int fh;
static int nodriver=0;
+ unsigned long *ptr = (unsigned long *) buffer;
if (nodriver==1)
return 0;
@@ -80,14 +81,13 @@
(void)snprintf(cpuname, sizeof(cpuname), "/dev/cpu/%d/msr", cpu);
fh = open(cpuname, O_RDONLY);
- if (fh==-1) {
- if (!silent)
- perror(cpuname);
+ if (fh == -1) {
+ perror(cpuname);
nodriver=1;
return 0;
}
- if (lseek(fh, idx, SEEK_CUR)==-1) {
+ if (lseek64(fh, (off64_t) idx, SEEK_CUR) == -1) {
perror("lseek");
exit(EXIT_FAILURE);
}
@@ -101,12 +101,12 @@
return 0;
}
- lo = (*(unsigned long *)buffer);
- hi = (*(unsigned long *)(buffer+4));
+ lo = *(ptr)++;
+ hi = *(ptr);
*val = hi;
*val = (*val<<32) | lo;
}
- if (close(fh)==-1) {
+ if (close(fh) == -1) {
perror("close");
exit(EXIT_FAILURE);
}
@@ -121,11 +121,11 @@
unsigned long long val=0;
if (read_msr(cpu, msr, &val) == 1) {
- if (size==32){
+ if (size == 32){
printf("MSR: 0x%08x=0x%08lx : ", msr, (unsigned long) val);
binary32(val);
}
- if (size==64) {
+ if (size == 64) {
printf("MSR: 0x%08x=0x%016llx : ", msr, val);
binary64(val);
}
@@ -139,9 +139,9 @@
unsigned long long val=0;
if (read_msr(cpu, msr, &val) == 1) {
- if (size==32)
+ if (size == 32)
binary32(val);
- if (size==64)
+ if (size == 64)
binary64(val);
return;
}
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/results/Intel/core2-duo-E2180.txt
^
|
| @@ -0,0 +1,338 @@
+x86info v1.24. Dave Jones 2001-2009
+Feedback to <davej@redhat.com>.
+
+Found 2 CPUs
+MP Table:
+# APIC ID Version State Family Model Step Flags
+# 0 0x14 BSP, usable 6 15 13 0xbfebfbff
+# 1 0x14 AP, usable 6 15 13 0xbfebfbff
+
+--------------------------------------------------------------------------
+CPU #1
+EFamily: 0 EModel: 0 Family: 6 Model: 15 Stepping: 13
+CPU Model: Core 2 Duo [M0]
+Processor name string: Intel(R) Pentium(R) Dual CPU E2180 @ 2.00GHz
+Type: 0 (Original OEM) Brand: 0 (Unsupported)
+
+Number of reporting banks : 6
+
+Erk, MCG_CTL not present! :0000000000000806:
+
+Bank: 0 (0x400)
+MC0CTL: 00000000 00000000 00000000 00000000
+ 01000010 10001000 00000000 00000000
+MC0STATUS: 00010000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC0ADDR: 00000000 00000000 00000000 00000000
+ 00110100 11100111 01010101 01000000
+
+Bank: 1 (0x404)
+MC1CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC1STATUS: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC1ADDR: 00000000 00000000 00000010 10101001
+ 00000000 00000000 00000010 10101001
+
+Bank: 2 (0x408)
+MC2CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC2STATUS: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC2ADDR: 00000000 00000000 00000010 10101001
+ 00000000 00000000 00000010 10101001
+
+Bank: 3 (0x40c)
+MC3CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC3STATUS: 00000000 00100000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC3ADDR: 00000000 00000000 00000000 00000010
+ 00101000 00001000 00000100 00110000
+
+Bank: 4 (0x410)
+MC4CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00001000
+MC4STATUS: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00010001
+MC4ADDR: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+
+Bank: 5 (0x414)
+MC5CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC5STATUS: 00010000 00000000 00000000 00010000
+ 00000100 00000000 00001110 00001111
+MC5ADDR: Couldn't read MSR 0x416
+
+Microcode version: 0x00000000000000a3
+
+Number of cores per physical package=2
+Number of logical processors per socket=2
+Number of logical processors per core=1
+APIC ID: 0x0 Package: 0 Core: 0 SMT ID 0
+eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69
+eax in: 0x00000001, eax = 000006fd ebx = 00020800 ecx = 0000e39d edx = bfebfbff
+eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb43078
+eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x00000004, eax = 04000121 ebx = 01c0003f ecx = 0000003f edx = 00000001
+eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000220
+eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000
+eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000503
+
+eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100000
+eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 6e655020 edx = 6d756974
+eax in: 0x80000003, eax = 20295228 ebx = 6c617544 ecx = 50432020 edx = 45202055
+eax in: 0x80000004, eax = 30383132 ebx = 20402020 ecx = 30302e32 edx = 007a4847
+eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 04004040 edx = 00000000
+eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000
+
+Cache info
+ L1 Instruction cache: 32KB, 8-way associative. 64 byte line size.
+ L1 Data cache: 32KB, 8-way associative. 64 byte line size.
+ L2 cache: 1MB, sectored, 8-way associative. 64 byte line size.
+TLB info
+ Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative
+ Instruction TLB: 4K pages, 4-way associative, 128 entries.
+ Data TLB: 4MB pages, 4-way associative, 32 entries
+ L1 Data TLB: 4KB pages, 4-way set associative, 16 entries
+ L1 Data TLB: 4MB pages, 4-way set associative, 16 entries
+ Data TLB: 4K pages, 4-way associative, 256 entries.
+ 64 byte prefetching.
+Feature flags:
+ Onboard FPU
+ Virtual Mode Extensions
+ Debugging Extensions
+ Page Size Extensions
+ Time Stamp Counter
+ Model-Specific Registers
+ Physical Address Extensions
+ Machine Check Architecture
+ CMPXCHG8 instruction
+ Onboard APIC
+ SYSENTER/SYSEXIT
+ Memory Type Range Registers
+ Page Global Enable
+ Machine Check Architecture
+ CMOV instruction
+ Page Attribute Table
+ 36-bit PSEs
+ CLFLUSH instruction
+ Debug Trace Store
+ ACPI via MSR
+ MMX support
+ FXSAVE and FXRESTORE instructions
+ SSE support
+ SSE2 support
+ CPU self snoop
+ Hyper-Threading
+ Thermal Monitor
+ Pending Break Enable
+
+Extended feature flags:
+ sse3 [2] monitor ds-cpl est tm2 ssse3 cx16 xTPR [15]
+
+MTRR registers:
+MTRRcap (0xfe): 0x0000000000000508
+MTRRphysBase0 (0x200): 0x0000000000000006
+MTRRphysMask0 (0x201): 0x0000000f80000800
+MTRRphysBase1 (0x202): 0x0000000080000006
+MTRRphysMask1 (0x203): 0x0000000fc0000800
+MTRRphysBase2 (0x204): 0x0000000000000000
+MTRRphysMask2 (0x205): 0x0000000000000000
+MTRRphysBase3 (0x206): 0x0000000000000000
+MTRRphysMask3 (0x207): 0x0000000000000000
+MTRRphysBase4 (0x208): 0x0000000000000000
+MTRRphysMask4 (0x209): 0x0000000000000000
+MTRRphysBase5 (0x20a): 0x0000000000000000
+MTRRphysMask5 (0x20b): 0x0000000000000000
+MTRRphysBase6 (0x20c): 0x0000000000000000
+MTRRphysMask6 (0x20d): 0x0000000000000000
+MTRRphysBase7 (0x20e): 0x0000000000000000
+MTRRphysMask7 (0x20f): 0x0000000000000000
+MTRRfix64K_00000 (0x250): 0x0606060606060606
+MTRRfix16K_80000 (0x258): 0x0606060606060606
+MTRRfix16K_A0000 (0x259): 0x0000000000000000
+MTRRfix4K_C8000 (0x269): 0x0000000000000000
+MTRRfix4K_D0000 0x26a: 0x0000000000000000
+MTRRfix4K_D8000 0x26b: 0x0000000000000000
+MTRRfix4K_E0000 0x26c: 0x0404040404040404
+MTRRfix4K_E8000 0x26d: 0x0404040404040404
+MTRRfix4K_F0000 0x26e: 0x0505050505050505
+MTRRfix4K_F8000 0x26f: 0x0505050505050505
+MTRRdefType (0x2ff): 0x0000000000000c00
+
+
+2.00GHz processor (estimate).
+
+--------------------------------------------------------------------------
+CPU #2
+EFamily: 0 EModel: 0 Family: 6 Model: 15 Stepping: 13
+CPU Model: Core 2 Duo [M0]
+Processor name string: Intel(R) Pentium(R) Dual CPU E2180 @ 2.00GHz
+Type: 0 (Original OEM) Brand: 0 (Unsupported)
+
+Number of reporting banks : 6
+
+Erk, MCG_CTL not present! :0000000000000806:
+
+Bank: 0 (0x400)
+MC0CTL: 00000000 00000000 00000000 00000000
+ 01000010 10001000 00000000 00000000
+MC0STATUS: 00010000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC0ADDR: 00000000 00000000 00000000 00000000
+ 00000000 01001110 10101011 11000000
+
+Bank: 1 (0x404)
+MC1CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC1STATUS: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC1ADDR: 00000000 00000000 00000010 10101001
+ 00000000 00000000 00000010 10101001
+
+Bank: 2 (0x408)
+MC2CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC2STATUS: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC2ADDR: 00000000 00000000 00000010 10101001
+ 00000000 00000000 00000010 10101001
+
+Bank: 3 (0x40c)
+MC3CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC3STATUS: 00000000 00100000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+MC3ADDR: 00000000 00000000 00000000 00000010
+ 00101000 00001000 00000100 00110000
+
+Bank: 4 (0x410)
+MC4CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00001000
+MC4STATUS: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00010001
+MC4ADDR: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000000
+
+Bank: 5 (0x414)
+MC5CTL: 00000000 00000000 00000000 00000000
+ 00000000 00000000 00000000 00000001
+MC5STATUS: 00010000 00000000 00000000 00010000
+ 00000000 00000000 00001110 00001111
+MC5ADDR: Couldn't read MSR 0x416
+
+Microcode version: 0x00000000000000a3
+
+Number of cores per physical package=2
+Number of logical processors per socket=2
+Number of logical processors per core=1
+APIC ID: 0x1 Package: 0 Core: 0 SMT ID 1
+eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69
+eax in: 0x00000001, eax = 000006fd ebx = 01020800 ecx = 0000e39d edx = bfebfbff
+eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb43078
+eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x00000004, eax = 04000121 ebx = 01c0003f ecx = 0000003f edx = 00000001
+eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000220
+eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000
+eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000503
+
+eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100000
+eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 6e655020 edx = 6d756974
+eax in: 0x80000003, eax = 20295228 ebx = 6c617544 ecx = 50432020 edx = 45202055
+eax in: 0x80000004, eax = 30383132 ebx = 20402020 ecx = 30302e32 edx = 007a4847
+eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 04004040 edx = 00000000
+eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
+eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000
+
+Cache info
+ L1 Instruction cache: 32KB, 8-way associative. 64 byte line size.
+ L1 Data cache: 32KB, 8-way associative. 64 byte line size.
+ L2 cache: 1MB, sectored, 8-way associative. 64 byte line size.
+TLB info
+ Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative
+ Instruction TLB: 4K pages, 4-way associative, 128 entries.
+ Data TLB: 4MB pages, 4-way associative, 32 entries
+ L1 Data TLB: 4KB pages, 4-way set associative, 16 entries
+ L1 Data TLB: 4MB pages, 4-way set associative, 16 entries
+ Data TLB: 4K pages, 4-way associative, 256 entries.
+ 64 byte prefetching.
+Feature flags:
+ Onboard FPU
+ Virtual Mode Extensions
+ Debugging Extensions
+ Page Size Extensions
+ Time Stamp Counter
+ Model-Specific Registers
+ Physical Address Extensions
+ Machine Check Architecture
+ CMPXCHG8 instruction
+ Onboard APIC
+ SYSENTER/SYSEXIT
+ Memory Type Range Registers
+ Page Global Enable
+ Machine Check Architecture
+ CMOV instruction
+ Page Attribute Table
+ 36-bit PSEs
+ CLFLUSH instruction
+ Debug Trace Store
+ ACPI via MSR
+ MMX support
+ FXSAVE and FXRESTORE instructions
+ SSE support
+ SSE2 support
+ CPU self snoop
+ Hyper-Threading
+ Thermal Monitor
+ Pending Break Enable
+
+Extended feature flags:
+ sse3 [2] monitor ds-cpl est tm2 ssse3 cx16 xTPR [15]
+
+MTRR registers:
+MTRRcap (0xfe): 0x0000000000000508
+MTRRphysBase0 (0x200): 0x0000000000000006
+MTRRphysMask0 (0x201): 0x0000000f80000800
+MTRRphysBase1 (0x202): 0x0000000080000006
+MTRRphysMask1 (0x203): 0x0000000fc0000800
+MTRRphysBase2 (0x204): 0x0000000000000000
+MTRRphysMask2 (0x205): 0x0000000000000000
+MTRRphysBase3 (0x206): 0x0000000000000000
+MTRRphysMask3 (0x207): 0x0000000000000000
+MTRRphysBase4 (0x208): 0x0000000000000000
+MTRRphysMask4 (0x209): 0x0000000000000000
+MTRRphysBase5 (0x20a): 0x0000000000000000
+MTRRphysMask5 (0x20b): 0x0000000000000000
+MTRRphysBase6 (0x20c): 0x0000000000000000
+MTRRphysMask6 (0x20d): 0x0000000000000000
+MTRRphysBase7 (0x20e): 0x0000000000000000
+MTRRphysMask7 (0x20f): 0x0000000000000000
+MTRRfix64K_00000 (0x250): 0x0606060606060606
+MTRRfix16K_80000 (0x258): 0x0606060606060606
+MTRRfix16K_A0000 (0x259): 0x0000000000000000
+MTRRfix4K_C8000 (0x269): 0x0000000000000000
+MTRRfix4K_D0000 0x26a: 0x0000000000000000
+MTRRfix4K_D8000 0x26b: 0x0000000000000000
+MTRRfix4K_E0000 0x26c: 0x0404040404040404
+MTRRfix4K_E8000 0x26d: 0x0404040404040404
+MTRRfix4K_F0000 0x26e: 0x0505050505050505
+MTRRfix4K_F8000 0x26f: 0x0505050505050505
+MTRRdefType (0x2ff): 0x0000000000000c00
+
+
+4154502.40GHz processor (estimate).
+
+--------------------------------------------------------------------------
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/scripts/makenodes
^
|
| @@ -1,6 +1,15 @@
#!/bin/bash
-NRNODES=`grep processor /proc/cpuinfo | wc -l`
+# Only root can run this script
+if [ "$(id -u)" != "0" ]; then
+ echo "This script must be run as root" 1>&2
+ exit 1
+fi
+
+let NRNODES=(`grep processor /proc/cpuinfo | wc -l`)-1
+
+loadCpuid=0
+loadMsr=0
if [ ! -d /dev/cpu ] ; then
mkdir /dev/cpu
@@ -13,10 +22,19 @@
fi
if [ ! -c /dev/cpu/$i/cpuid ] ; then
(cd /dev/cpu/$i ; mknod cpuid c 203 $i)
+ loadCpuid=1
fi
if [ ! -c /dev/cpu/$i/msr ] ; then
(cd /dev/cpu/$i ; mknod msr c 202 $i)
+ loadMsr=1
fi
done
+if test "$loadCpuid" -eq 1 ; then
+ modprobe cpuid
+fi
+if test "$loadMsr" -eq 1 ; then
+ modprobe msr
+fi
+
echo "All cpuid & msr /dev nodes present."
|
|
[-]
[+]
|
Added |
x86info-1.29.tar.bz2/topology.c
^
|
| @@ -0,0 +1,117 @@
+/*
+ * (C) 2011 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "x86info.h"
+
+static char * corenum(int num)
+{
+ switch (num) {
+ case 1: return ("single");
+ case 2: return ("dual");
+ case 3: return ("tri");
+ case 4: return ("quad");
+ case 6: return ("six");
+ case 8: return ("eight");
+ default:
+ return ("?");
+ }
+}
+
+void get_topology(struct cpudata *cpu)
+{
+ if (cpu->vendor == VENDOR_INTEL)
+ get_intel_topology(cpu);
+}
+
+void display_topology(struct cpudata *head)
+{
+ struct cpudata *cpu;
+ unsigned int threads_per_socket;
+ unsigned int i;
+ char *sockets;
+
+ int num_sockets = 0;
+
+ /* For now, we only support topology parsing on Intel. */
+ if (head->vendor != VENDOR_INTEL)
+ return;
+
+ if (debug == 1) {
+ cpu = head;
+ printf("cpu->phys_proc_id: ");
+ for (i = 0; i < nrCPUs; i++) {
+ printf("%d, ", cpu->phys_proc_id);
+ cpu = cpu->next;
+ }
+ printf("\n");
+
+ cpu = head;
+ printf("cpu->x86_max_cores: ");
+ for (i = 0; i < nrCPUs; i++) {
+ printf("%d, ", cpu->x86_max_cores);
+ cpu = cpu->next;
+ }
+ printf("\n");
+
+ cpu = head;
+ printf("cpu->cpu_core_id: ");
+ for (i = 0; i < nrCPUs; i++) {
+ printf("%d, ", cpu->cpu_core_id);
+ cpu = cpu->next;
+ }
+ printf("\n");
+ }
+
+ sockets = malloc(nrCPUs);
+ if (sockets == NULL)
+ return;
+
+ for (i = 0; i < nrCPUs; i++)
+ sockets[i]=0;
+
+ cpu = head;
+ for (i = 0; i < nrCPUs; i++) {
+ sockets[cpu->phys_proc_id]++;
+ cpu = cpu->next;
+ }
+
+ for (i = 0; i < nrCPUs; i++) {
+ if (debug == 1)
+ printf("Socket %d: %d threads\n", i, sockets[i]);
+ if (sockets[i] != 0) /* only count populated sockets */
+ num_sockets++;
+ }
+
+ /* Print a topology summary */
+ cpu = head;
+ printf("Total processor threads: %d\n", sockets[0] * num_sockets);
+ printf("This system has %d ", num_sockets);
+ threads_per_socket = sockets[0];
+ if (cpu->flags_edx & X86_FEATURE_HT)
+ if (cpu->num_siblings > 1)
+ threads_per_socket = sockets[0]/2;
+
+ if (nrCPUs == 1) {
+ /* Handle the single CPU case */
+ printf("processor");
+ } else {
+ char *p;
+ p = corenum(threads_per_socket);
+
+ if (strncmp("?", p, 1))
+ printf("%s-core processor", corenum(threads_per_socket));
+ else
+ printf("%d-core processor", threads_per_socket);
+ if (num_sockets > 1)
+ printf("s");
+ }
+
+ if (cpu->flags_edx & X86_FEATURE_HT && cpu->num_siblings > 1)
+ printf(" with hyper-threading (%d threads per core)", cpu->num_siblings);
+}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/x86info.1
^
|
| @@ -92,7 +92,7 @@
Dump MP table showing CPUs BIOS knows about.
.IP "\fB-r\fP \fB--registers\fP " 10
Show register values from all possible cpuid calls.
-.IP "\fB-s\fP \fB--show-bluesmoke\fP " 10
+.IP "\fB-s\fP \fB--show-machine-check\fP " 10
Show machine check exception information.
.IP "\fB-v\fP \fB--verbose\fP " 10
Show verbose descriptions.
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/x86info.c
^
|
| @@ -1,5 +1,5 @@
/*
- * (C) 2001-2009 Dave Jones.
+ * (C) 2001-2011 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*/
@@ -14,204 +14,176 @@
#include "Intel/Intel.h"
-int show_bench=0;
-int show_bios=0;
-int show_bluesmoke=0;
-int show_bugs=0;
-int show_cacheinfo=0;
-int show_connector=0;
-int show_eblcr=0;
-int show_msr=0;
-int show_microcode=0;
-int show_mtrr=0;
-int show_pm=0;
-int show_registers=0;
-int show_urls=0;
-
-static int show_mptable=0;
-static int show_flags=0;
-static int show_MHz=0;
-
-int verbose=0;
-int silent = 0;
-int used_UP = 0;
-int user_is_root = 1;
-static int need_root = 0;
+unsigned int user_is_root = 0;
unsigned int nrCPUs=1;
static unsigned int nrSMPCPUs;
-static void usage (char *programname)
+struct cpudata *firstcpu;
+
+
+static void separator(void)
{
- printf("Usage: %s [<switches>]\n\
--a, --all\n\
- --bench\n\
- --bios\n\
- --bugs\n\
--c, --cache\n\
- --connector\n\
--f, --flags\n\
--mhz, --mhz\n\
- --microcode\n\
--mp, --mptable\n\
--m, --msr\n\
- --mult\n\
- --mtrr\n\
- --pm\n\
--r, --registers\n\
--s, --show-bluesmoke\n\
--u, --urls\n\
--v, --verbose\n\
-\n", programname);
- exit (0);
+ int j;
+
+ for (j = 0; j < 74; j++)
+ printf("-");
+ printf("\n");
}
-static void parse_command_line (int argc, char **argv)
+
+static void display_detailed_info(struct cpudata *cpu)
{
- char **argp, *arg;
+ bind_cpu(cpu); /* FIXME: Eventually remove once 'gather' has all the per-cpu stuff */
+ show_info(cpu);
- for (argp = argv+1; argp <= argv + argc && (arg = *argp); argp++) {
- if ((!strcmp(arg, "-a") || !strcmp(arg, "--all"))) {
-// show_bench = 1;
- show_bios = 1;
- show_bluesmoke = 1;
- show_bugs = 1;
- show_cacheinfo = 1;
- show_connector = 1;
- show_eblcr =1;
- show_flags = 1;
- show_microcode = 1;
- show_mptable =1;
- show_msr = 1;
- show_MHz = 1;
- show_mtrr = 1;
- show_pm = 1;
- show_registers = 1;
- show_urls = 1;
- need_root = 1;
- }
+ if (show_cpuid) {
+ dump_raw_cpuid(cpu->number, 0, cpu->cpuid_level);
+ if (cpu->maxei >=0x80000000)
+ dump_raw_cpuid(cpu->number, 0x80000000, cpu->maxei);
- if (!strcmp(arg, "--bench"))
- show_bench = 1;
+ if (cpu->maxei2 >=0xC0000000)
+ dump_raw_cpuid(cpu->number, 0xC0000000, cpu->maxei2);
+ }
- if (!strcmp(arg, "--bios")) {
- need_root = 1;
- show_bios = 1;
+ if (show_cacheinfo) {
+ switch (cpu->vendor) {
+ case VENDOR_INTEL:
+ decode_Intel_caches(cpu, 1);
+ break;
+ case VENDOR_AMD:
+ decode_AMD_cacheinfo(cpu);
+ break;
+ default:
+ break;
}
+ }
- if (!strcmp(arg, "--bugs"))
- show_bugs = 1;
-
- if ((!strcmp(arg, "-c") || !strcmp(arg, "--cache")))
- show_cacheinfo = 1;
-
- if (!strcmp(arg, "--connector"))
- show_connector = 1;
+ if (show_feature_flags)
+ display_feature_flags(cpu);
- if ((!strcmp(arg, "-f") || !strcmp(arg, "--flags")))
- show_flags = 1;
+ if (show_connector)
+ decode_connector(cpu->connector);
- if ((!strcmp(arg, "-m") || !strcmp(arg, "--msr"))) {
- need_root = 1;
- show_msr = 1;
- }
+ if (show_urls) {
+ if (cpu->info_url != NULL)
+ printf("Info URL: %s\n", cpu->info_url);
+ if (cpu->datasheet_url != NULL)
+ printf("Datasheet: %s\n", cpu->datasheet_url);
+ if (cpu->errata_url != NULL)
+ printf("Errata: %s\n", cpu->errata_url);
+ }
- if (!strcmp(arg, "--microcode")) {
- need_root = 1;
- show_microcode = 1;
- }
+ /* Info that requires root access (eg, reading MSRs etc) */
+ if (user_is_root) {
+ if (show_mtrr)
+ dump_mtrrs(cpu);
- if ((!strcmp(arg, "-mhz") || !strcmp(arg, "--mhz")))
- show_MHz = 1;
+ if (show_apic)
+ dump_apics(cpu);
+ }
- if ((!strcmp(arg, "-mp") || !strcmp(arg, "--mptable"))) {
- need_root = 1;
- show_mptable = 1;
- }
+ if (show_addr_sizes)
+ printf("Address sizes : %u bits physical, %u bits virtual\n",
+ cpu->phyaddr_bits, cpu->viraddr_bits);
+
+ if (show_MHz) {
+ display_MHz(cpu);
+ printf(" processor (estimate).\n\n");
+ }
- if (!strcmp(arg, "--mtrr")) {
- need_root = 1;
- show_mtrr = 1;
- }
+ if (show_bench)
+ show_benchmarks(cpu);
+}
- if (!strcmp(arg, "--mult")) {
- need_root = 1;
- show_eblcr = 1;
- }
+/*
+ * check to see if all CPUs are the same.
+ * returns 1 if all cpus are the same, 0 if something is different
+ */
+static int check_cpu_similarity()
+{
+ struct cpudata *cpu;
+ unsigned int i;
- if (!strcmp(arg, "--pm"))
- show_pm = 1;
+ /* force to display all cpus if the user requested it. */
+ if (all_cpus)
+ return 0;
- if ((!strcmp(arg, "-r") || !strcmp(arg, "--registers")))
- show_registers = 1;
+ if (nrCPUs == 1)
+ return 1;
- if ((!strcmp(arg, "-s") || !strcmp(arg, "--show-bluesmoke"))) {
- need_root = 1;
- show_bluesmoke = 1;
- }
+ cpu = firstcpu;
+ for (i = 0; i < nrCPUs; i++) {
+ cpu = cpu->next;
+ if (!cpu)
+ return 1;
+
+ if (cpu->efamily != firstcpu->efamily)
+ return 0;
+ if (cpu->emodel != firstcpu->emodel)
+ return 0;
+ if (cpu->family != firstcpu->family)
+ return 0;
+ if (model(cpu) != model(firstcpu))
+ return 0;
+ if (cpu->stepping != firstcpu->stepping)
+ return 0;
+ }
- if ((!strcmp(arg, "-u") || !strcmp(arg, "--urls")))
- show_urls = 1;
+ return 1;
+}
- if ((!strcmp(arg, "-v") || !strcmp(arg, "--verbose")))
- verbose = 1;
+static struct cpudata *alloc_cpu()
+{
+ struct cpudata *newcpu;
- if ((!strcmp(arg, "?") || !strcmp(arg, "--help")))
- usage(argv[0]);
+ newcpu = malloc (sizeof (struct cpudata));
+ if (!newcpu) {
+ printf("Out of memory\n");
+ exit(EXIT_FAILURE);
}
-}
+ memset(newcpu, 0, sizeof(struct cpudata));
+ return newcpu;
+}
-static void separator(void)
+static void fill_in_cpu_info(struct cpudata *cpu)
{
- int j;
-
- for (j=0; j<74; j++)
- printf("-");
- printf("\n");
+ bind_cpu(cpu);
+ estimate_MHz(cpu);
+ get_cpu_info_basics(cpu); /* get vendor,family,model,stepping */
+ get_feature_flags(cpu);
+ identify(cpu);
+ get_topology(cpu);
}
int main (int argc, char **argv)
{
+ struct cpudata *cpu=NULL, *tmp;
unsigned int i;
- struct cpudata *cpu, *head=NULL, *tmp;
+ unsigned int display_one_cpu = 1;
+
+ if (getuid() == 0)
+ user_is_root = 1;
parse_command_line(argc, argv);
- if (!silent) {
- printf("x86info v1.24. Dave Jones 2001-2009\n");
- printf("Feedback to <davej@redhat.com>.\n\n");
- }
+
+ printf("x86info v1.29. Dave Jones 2001-2011\n");
+ printf("Feedback to <davej@redhat.com>.\n\n");
if ((HaveCPUID()) == 0) {
printf("No CPUID instruction available.\n");
printf("No further information available for this CPU.\n");
- return 0;
+ exit(EXIT_SUCCESS);
}
- if (getuid() != 0)
- user_is_root=0;
-
- if (need_root && !user_is_root)
+ if (need_root && !user_is_root) {
printf("Need to be root to use specified options.\n");
-
- nrCPUs = sysconf(_SC_NPROCESSORS_ONLN);
-
- if (!silent) {
- printf("Found %u CPU", nrCPUs);
- if (nrCPUs > 1)
- printf("s");
-
- /* Check mptable if present. This way we get number of CPUs
- on SMP systems that have booted UP kernels. */
- if (user_is_root) {
- nrSMPCPUs = enumerate_cpus();
- if (nrSMPCPUs > nrCPUs)
- printf(", but found %ud CPUs in MPTable.", nrSMPCPUs);
- }
- printf("\n");
+ exit(EXIT_FAILURE);
}
+ nrCPUs = sysconf(_SC_NPROCESSORS_ONLN);
/*
* can't have less than 1 CPU, or more than
* 65535 (some arbitrary large number)
@@ -221,109 +193,70 @@
nrCPUs = 1;
}
- if (show_mptable && user_is_root)
- (void)issmp(1); // FIXME: issmp should become 'show_mptable'
-
- separator();
-
- /* Iterate over the linked list. */
-
- for (i=0; i<nrCPUs; i++) {
- cpu = malloc (sizeof (struct cpudata));
- if (!cpu) {
- printf("Out of memory\n");
- return -1;
- }
-
- memset(cpu, 0, sizeof(struct cpudata));
+ /* Allocate a cpu for boot cpu. */
+ cpu = firstcpu = alloc_cpu();
+ fill_in_cpu_info(cpu);
+
+ /* Allocate structs for non-boot CPUs if present */
+ if (nrCPUs > 1) {
+ for (i = 1; i < nrCPUs; i++) {
+ cpu->next = alloc_cpu();
+ cpu = cpu->next;
+ cpu->number = i;
- if (!head) {
- head = cpu;
- } else {
- cpu->next = head;
- head = cpu;
+ fill_in_cpu_info(cpu);
}
+ }
- cpu->number = i;
+ display_one_cpu = check_cpu_similarity();
- if (!silent && nrCPUs != 1)
- printf("CPU #%u\n", i+1);
+ if (show_mptable && user_is_root)
+ display_mptable();
- bind_cpu(cpu);
+ /* Now we display the info we gathered */
+ cpu = firstcpu;
- estimate_MHz(cpu);
- get_feature_flags(cpu);
- get_cpu_info_basics(cpu); /* get vendor,family,model,stepping */
- identify(cpu);
- show_info(cpu);
-
- if (show_registers) {
- dumpregs(cpu->number, 0, cpu->maxi);
- if (cpu->maxei >=0x80000000)
- dumpregs (cpu->number, 0x80000000, cpu->maxei);
+ if (display_one_cpu) {
+ if (nrCPUs >= 2)
+ printf("Found %d identical CPUs", nrCPUs);
- if (cpu->maxei2 >=0xC0000000)
- dumpregs (cpu->number, 0xC0000000, cpu->maxei2);
- }
+ /* Check mptable if present. This way we get number of CPUs
+ on SMP systems that have booted UP kernels. */
+ if (user_is_root) {
+ nrSMPCPUs = enumerate_cpus();
- if (show_cacheinfo == 1) {
- switch (cpu->vendor) {
- case VENDOR_INTEL:
- decode_Intel_caches(cpu, 1);
- break;
- case VENDOR_AMD:
- decode_AMD_cacheinfo(cpu);
- break;
- default:
- break;
- }
+ if (nrSMPCPUs > nrCPUs)
+ printf(" (but found %ud CPUs in MPTable!)", nrSMPCPUs);
}
+ if (nrCPUs >= 2)
+ printf("\n");
- if (show_flags == 1)
- show_feature_flags(cpu);
-
- if (show_connector)
- decode_connector(cpu->connector);
+ display_detailed_info(cpu);
+ } else {
+ printf("Found %d CPUs.\n", nrCPUs);
+ for (i = 0; i < nrCPUs; i++) {
+ printf("CPU #%u:\n", i+1);
- if (show_urls) {
- if (cpu->datasheet_url != NULL)
- printf("Datasheet: %s\n", cpu->datasheet_url);
- if (cpu->errata_url != NULL)
- printf("Errata: %s\n", cpu->errata_url);
- }
+ display_detailed_info(cpu);
- /* Info that requires root access (eg, reading MSRs etc) */
- if (user_is_root) {
- if (show_mtrr)
- dump_mtrrs(cpu);
+ if (nrCPUs > 1)
+ separator();
+ cpu = cpu->next;
}
+ }
- /* Show MHz last. */
- if (show_MHz) {
- if (cpu->MHz < 1000)
- printf("%uMHz", cpu->MHz);
- else {
- int a = (cpu->MHz / 1000);
- int b = ((cpu->MHz % 1000)/100);
- int c = (a*1000)+(b*100);
-
- printf("%u.%u%uGHz", a, b, (cpu->MHz - c)/10);
- }
- printf(" processor (estimate).\n\n");
- }
- if (show_bench)
- show_benchmarks(cpu);
+ display_topology(firstcpu);
- if (nrCPUs > 1)
- separator();
+ printf(" running at an estimated ");
+ display_MHz(firstcpu);
+ printf("\n");
- if (cpu->next)
- cpu = cpu->next;
- }
/* Tear down the linked list. */
- cpu = head;
- for (i=0; i<nrCPUs; i++) {
+ cpu = firstcpu;
+ for (i = 0; i < nrCPUs; i++) {
+ if (cpu->info_url)
+ free(cpu->info_url);
if (cpu->datasheet_url)
free(cpu->datasheet_url);
if (cpu->errata_url)
@@ -333,10 +266,5 @@
cpu = tmp;
}
- if (nrCPUs > 1 && (used_UP == 1) && (!silent)) {
- printf("WARNING: Detected SMP, but unable to access cpuid driver.\n");
- printf("Used Uniprocessor CPU routines. Results inaccurate.\n");
- }
-
- return (0);
+ exit(EXIT_SUCCESS);
}
|
|
[-]
[+]
|
Changed |
x86info-1.29.tar.bz2/x86info.h
^
|
| @@ -1,8 +1,6 @@
#ifndef _X86INFO_H
#define _X86INFO_H
-#include "cpuid.h"
-
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
@@ -54,8 +52,12 @@
CONN_SOCKET_AM2,
CONN_SOCKET_S1G1,
CONN_SOCKET_S1G2,
+ CONN_SOCKET_S1G3,
CONN_SOCKET_F_R2,
- CONN_SOCKET_AM2_R2,
+ CONN_SOCKET_AM3,
+ CONN_SOCKET_G34,
+ CONN_SOCKET_ASB2,
+ CONN_SOCKET_C32,
};
#define CPU_NAME_LEN 80
@@ -73,7 +75,9 @@
unsigned int cachesize_L2;
unsigned int cachesize_L3;
unsigned int cachesize_trace;
- unsigned int maxi, maxei, maxei2;
+ unsigned int phyaddr_bits;
+ unsigned int viraddr_bits;
+ unsigned int cpuid_level, maxei, maxei2;
char name[CPU_NAME_LEN];
enum connector connector;
unsigned int flags_ecx;
@@ -83,14 +87,32 @@
unsigned int MHz;
unsigned int nr_cores;
unsigned int nr_logical;
+ char *info_url;
char *datasheet_url;
char *errata_url;
/* Intel specific bits */
unsigned int brand;
unsigned int apicid;
char serialno[30];
+
+ unsigned int phys_proc_id;
+ unsigned int initial_apicid;
+ unsigned int x86_max_cores;
+ unsigned int cpu_core_id;
+ unsigned int num_siblings;
};
+void cpuid_UP(unsigned int idx,
+ unsigned long *eax, unsigned long *ebx, unsigned long *ecx, unsigned long *edx);
+void cpuid(unsigned int cpu, unsigned long long idx,
+ unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
+void cpuid4(unsigned int CPU_number, unsigned long long idx,
+ unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
+void cpuid_count(unsigned int CPU_number, unsigned int op, int count,
+ unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx);
+unsigned int cpuid_ebx(unsigned int CPU_number, unsigned int op);
+
+
#define family(c) (c->family + c->efamily)
#define model(c) ((c->emodel << 4) + c->model)
@@ -109,70 +131,92 @@
return NULL; \
}
-extern void Identify_AMD (struct cpudata *cpu);
-extern void Identify_Cyrix (struct cpudata *cpu);
-extern void identify_centaur(struct cpudata *cpu);
-extern void Identify_Intel (struct cpudata *cpu);
-extern void identify_RiSE(struct cpudata *cpu);
-extern void identify_natsemi(struct cpudata *cpu);
-extern void identify_sis(struct cpudata *cpu);
-
-extern void display_AMD_info(struct cpudata *cpu);
-extern void display_Cyrix_info(struct cpudata *cpu);
-extern void display_centaur_info(struct cpudata *cpu);
-extern void display_Intel_info(struct cpudata *cpu);
-
-extern void get_feature_flags(struct cpudata *cpu);
-extern void show_feature_flags(struct cpudata *cpu);
-extern void get_cpu_info_basics(struct cpudata *cpu);
-extern void identify(struct cpudata *cpu);
-extern void show_info(struct cpudata *cpu);
-
-extern int read_msr(int cpu, unsigned int idx, unsigned long long *val);
-extern void binary(unsigned int n, unsigned long value);
-extern void binary32(unsigned long value);
-extern void binary64(unsigned long long value);
-extern void dumpmsr (int cpunum, unsigned int msr, int size);
-extern void dumpmsr_bin (int cpunum, unsigned int msr, int size);
-extern void dumpregs(int cpunum, unsigned int begin, unsigned int end);
-
-extern void dump_mtrrs (struct cpudata *cpu);
-
-extern void estimate_MHz(struct cpudata *cpu);
-extern int HaveCPUID(void);
-extern void interpret_eblcr(u32 lo);
-extern int enumerate_cpus(void);
-extern void get_model_name(struct cpudata *cpu);
-extern void decode_connector(enum connector type);
-extern void show_benchmarks(struct cpudata *cpu);
-extern void decode_serial_number(struct cpudata *cpu);
-
-extern void show_intel_topology(struct cpudata *cpu);
+void Identify_AMD(struct cpudata *cpu);
+void Identify_Cyrix(struct cpudata *cpu);
+void identify_centaur(struct cpudata *cpu);
+void Identify_Intel(struct cpudata *cpu);
+void identify_RiSE(struct cpudata *cpu);
+void identify_natsemi(struct cpudata *cpu);
+void identify_sis(struct cpudata *cpu);
+
+void display_AMD_info(struct cpudata *cpu);
+void display_Cyrix_info(struct cpudata *cpu);
+void display_centaur_info(struct cpudata *cpu);
+void display_basic_Intel_info(struct cpudata *cpu);
+void display_extended_Intel_info(struct cpudata *cpu);
+
+void get_feature_flags(struct cpudata *cpu);
+void display_feature_flags(struct cpudata *cpu);
+void show_extra_intel_flags(struct cpudata *cpu);
+
+void parse_command_line(int argc, char **argv);
+
+void get_cpu_info_basics(struct cpudata *cpu);
+void identify(struct cpudata *cpu);
+void show_info(struct cpudata *cpu);
+
+int read_msr(int cpu, unsigned int idx, unsigned long long *val);
+void binary(unsigned int n, unsigned long value);
+void binary32(unsigned long value);
+void binary64(unsigned long long value);
+void dumpmsr(int cpunum, unsigned int msr, int size);
+void dumpmsr_bin(int cpunum, unsigned int msr, int size);
+void dump_raw_cpuid(int cpunum, unsigned int begin, unsigned int end);
+
+void dump_mtrrs(struct cpudata *cpu);
+void dump_apics(struct cpudata *cpu);
+
+void display_MHz(struct cpudata *cpu);
+void estimate_MHz(struct cpudata *cpu);
+
+int HaveCPUID(void);
+void interpret_eblcr(u32 lo);
+int enumerate_cpus(void);
+void get_model_name(struct cpudata *cpu);
+void decode_connector(enum connector type);
+void show_benchmarks(struct cpudata *cpu);
+void decode_serial_number(struct cpudata *cpu);
+
+void get_topology(struct cpudata *head);
+void display_topology(struct cpudata *head);
+void get_intel_topology(struct cpudata *cpu);
void decode_AMD_cacheinfo(struct cpudata *cpu);
-extern int show_bench;
-extern int show_bios;
-extern int show_bluesmoke;
-extern int show_bugs;
-extern int show_cacheinfo;
-extern int show_connector;
-extern int show_eblcr;
-extern int verbose;
-extern int show_microcode;
-extern int show_msr;
-extern int show_mtrr;
-extern int show_pm;
-extern int show_registers;
-extern int show_urls;
-
extern unsigned int nrCPUs;
-extern int used_UP;
-extern int silent;
-extern int user_is_root;
+extern struct cpudata *firstcpu;
+
+extern unsigned int user_is_root;
+extern unsigned int need_root;
+
-#define X86_FEATURE_MTRR 1<<12
+/* command line args */
+extern unsigned int show_apic;
+extern unsigned int show_bench;
+extern unsigned int show_bios;
+extern unsigned int show_machine_check;
+extern unsigned int show_bugs;
+extern unsigned int show_cacheinfo;
+extern unsigned int show_connector;
+extern unsigned int show_eblcr;
+extern unsigned int show_msr;
+extern unsigned int show_microcode;
+extern unsigned int show_mtrr;
+extern unsigned int show_pm;
+extern unsigned int show_cpuid;
+extern unsigned int show_urls;
+extern unsigned int show_mptable;
+extern unsigned int show_feature_flags;
+extern unsigned int show_MHz;
+extern unsigned int show_addr_sizes;
+extern unsigned int all_cpus;
+extern unsigned int debug;
+extern unsigned int verbose;
+
+#define X86_FEATURE_HT (1<<28)
+#define X86_FEATURE_MTRR (1<<12)
+#define X86_FEATURE_APIC (1<<9)
#define _GNU_SOURCE
#define __USE_GNU
|
