Changes - j0ke.net Open Build Service

Changes of Revision 5

[-] [+]	Changed	flashrom.changes
@@ -1,4 +1,9 @@ ------------------------------------------------------------------- +Sa 9. Apr 22:03:25 CEST 2011 - cs@linux-administrator.com + +- update to 0.9.3 r1285. + +------------------------------------------------------------------- So 6. Feb 13:59:10 CET 2011 - cs@linux-administrator.com - update to 0.9.3 r1260.
[-] [+]	Changed	flashrom.spec ^
@@ -21,7 +21,7 @@ Name: flashrom Url: http://coreboot.org/ Summary: A universal flash programming utility -Version: 0.9.3_r1260 +Version: 0.9.3_r1285 Release: 1 License: GPL v2 only; GPL v2 or later Group: Development/Tools/Other
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/ChangeLog ^
@@ -1,4 +1,314 @@ ------------------------------------------------------------------------ +r1285 \| hailfinger \| 2011-04-02 13:47:21 +0200 (Sat, 02 Apr 2011) \| 8 lines + +List AMD SB850 as supported (it has the same PCI ID as SB700). + +Success report at +http://flashrom.org/pipermail/flashrom/2011-March/006072.html + +Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> +Acked-by: Idwer Vollering <vidwer@gmail.com> + +------------------------------------------------------------------------ +r1284 \| stepan \| 2011-04-01 20:05:20 +0200 (Fri, 01 Apr 2011) \| 5 lines + +coreboot table handling: make debug message msg_pdbg. + +Signed-off-by: Stefan Reinauer<stefan.reinauer@coreboot.org> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1283 \| stepan \| 2011-03-29 23:41:41 +0200 (Tue, 29 Mar 2011) \| 6 lines + +Fix typo in chipset_enable.c + +Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> +Acked-by: Idwer Vollering <vidwer@gmail.com> + + +------------------------------------------------------------------------ +r1282 \| stepan \| 2011-03-18 23:00:15 +0100 (Fri, 18 Mar 2011) \| 8 lines + +Update port of flashrom package to Mac OS X using DirectHW: +http://www.coreboot.org/DirectHW + +Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> + + +------------------------------------------------------------------------ +r1281 \| hailfinger \| 2011-03-17 01:10:25 +0100 (Thu, 17 Mar 2011) \| 11 lines + +Proper error handling for ICH/VIA SPI: +Use 16-bit values for bit masks in 16-bit registers. +Check for SPI Cycle In Progress and wait up to 60 ms. +Do not touch reserved bits. +Reduce SPI cycle timeout from 60 s to 60 ms. +Clear transaction errors caused by our own SPI accesses. +Add better debugging in case the hardware misbehaves. + +Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> + +------------------------------------------------------------------------ +r1280 \| oxygene \| 2011-03-08 08:17:44 +0100 (Tue, 08 Mar 2011) \| 12 lines + +Fix and improve libpayload platform support + +- Fix various minor compile issues (eg. include necessary standard headers) +- Fix compilation of libpayload code paths +- Provide libpayload support in Makefile +- Add make target "libflashrom.a" which links non-CLI code to static + library + +Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> +Tested-with-DOS-crosscompiler-by: Idwer Vollering <vidwer@gmail.com> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1279 \| hailfinger \| 2011-03-08 01:23:49 +0100 (Tue, 08 Mar 2011) \| 18 lines + +Various IT85* cleanups and fixes. + +Fix a few typos. +Change the EC memory region mapping name. +Drop unused function parameter. +Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory +locations instead of plain pointer access which is optimized away by gcc. +Use own it85_* SPI high-level chip read/write functions instead of +relying on unrelated ICH functions. + +Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +David writes: +I applied the patch against the Chromium OS branch and +successfully tested read and write operations on a Cr48. + +Acked-by: David Hendricks <dhendrix@google.com> + +------------------------------------------------------------------------ +r1278 \| hailfinger \| 2011-03-08 01:09:11 +0100 (Tue, 08 Mar 2011) \| 8 lines + +Fix compilation if CONFIG_INTERNAL=no. +Fix compilation if everything except CONFIG_SATAMV is no. +Do not compile in PCI support for wiki printing if no PCI devices are +supported. + +Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> + +------------------------------------------------------------------------ +r1277 \| hailfinger \| 2011-03-07 16:32:58 +0100 (Mon, 07 Mar 2011) \| 5 lines + +Fix broken compilation caused by a typo in r1275. + +Signed-off-by: Idwer Vollering <vidwer@gmail.com> +Acked-by: Idwer Vollering <vidwer@gmail.com> + +------------------------------------------------------------------------ +r1276 \| hailfinger \| 2011-03-07 11:59:06 +0100 (Mon, 07 Mar 2011) \| 5 lines + +Mark Macronix MX25L1605D as fully tested. + +Signed-off-by: Sven Schnelle <svens@stackframe.org> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1275 \| mkarcher \| 2011-03-07 02:09:55 +0100 (Mon, 07 Mar 2011) \| 6 lines + +SST39SF512 is tested + +flashrom -V -w: http://paste.flashrom.org/view.php?id=395 + +Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +------------------------------------------------------------------------ +r1274 \| hailfinger \| 2011-03-07 02:08:09 +0100 (Mon, 07 Mar 2011) \| 11 lines + +Simplify pcidev_init by killing the vendorid parameter which was pretty +useless anyway since it was present in the pcidevs parameter as well. + +This also allows us to handle multiple programmers with different vendor +IDs in the same driver. + +Fix compilation of flashrom with only the nicrealtek driver. + +Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> + +------------------------------------------------------------------------ +r1273 \| hailfinger \| 2011-03-06 23:52:55 +0100 (Sun, 06 Mar 2011) \| 11 lines + +Add a board enable for Asus P4P800-VM. + +Only list the memory controller PCI IDs because the only other subsystem +mentioned is used by network and sound interfaces both of which can be +turned off in BIOS. +Tested on a board rev 1.85. + +Signed-off-by: Diego Elio Petten?\195?\178 <flameeyes@gmail.com> +Acked-by: Idwer Vollering <vidwer@gmail.com> +Acked-by: Stefan Reinauer <stepan@coreboot.org> + +------------------------------------------------------------------------ +r1272 \| hailfinger \| 2011-03-06 23:26:23 +0100 (Sun, 06 Mar 2011) \| 6 lines + +Mark PMC Pm49FL004, SST SST49LF002A/B, SST SST49LF004A/B and +Winbond_W39V040FB as write tested. + +Signed-off-by: Idwer Vollering <vidwer@gmail.com> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1271 \| hailfinger \| 2011-03-06 23:16:30 +0100 (Sun, 06 Mar 2011) \| 7 lines + +Add Gigabyte GA-MA780G-UD3H to mainboard support list. + +http://www.flashrom.org/pipermail/flashrom/2010-October/005117.html + +Signed-off-by: Bernhard Geier <geierb@geierb.de> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1270 \| hailfinger \| 2011-03-06 19:45:40 +0100 (Sun, 06 Mar 2011) \| 7 lines + +Add support for ST M25PX16 and mark it as supported. +Tests were performed with write and verify operations to 4 different +M25PX16 chips with a Dediprog SF100. + +Signed-off-by: Carl Worth <carl.d.worth@intel.com> +Acked-by: Idwer Vollering <vidwer@gmail.com> + +------------------------------------------------------------------------ +r1269 \| hailfinger \| 2011-03-06 19:31:11 +0100 (Sun, 06 Mar 2011) \| 9 lines + +Mark SST49LF080A as fully tested. +Mark EVGA nForce 780i board as supported. + +Full logs are here: +http://www.flashrom.org/pipermail/flashrom/2011-January/005779.html + +Signed-off-by: Brandon Dowdy <brandonrd7@gmail.com> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1268 \| mkarcher \| 2011-03-06 18:58:05 +0100 (Sun, 06 Mar 2011) \| 4 lines + +Add W39L040 + +Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +------------------------------------------------------------------------ +r1267 \| mkarcher \| 2011-03-06 18:37:30 +0100 (Sun, 06 Mar 2011) \| 4 lines + +Add coreboot IDs to make manual selection of HP xw9400 possible + +Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +------------------------------------------------------------------------ +r1266 \| mkarcher \| 2011-03-06 13:09:05 +0100 (Sun, 06 Mar 2011) \| 15 lines + +Board-enable for GA-K8N51GMF + +Gigabyte is not really helpful with their PCI IDs for us, the subsystem +IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". +We should investigate whether autodetection of this board is causing +interference with other boards. + +real version 2: Extend list of PCI IDs for nvidia southbridges. + +flashrom -V: http://paste.flashrom.org/view.php?id=326 +lspic: http://paste.flashrom.org/view.php?id=328 +superiotool: http://paste.flashrom.org/view.php?id=329 + +Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +------------------------------------------------------------------------ +r1265 \| mkarcher \| 2011-03-06 13:07:19 +0100 (Sun, 06 Mar 2011) \| 11 lines + +Add HP e-Vectra P2706T + +Reported by: Michal Janke <jankeso@gmail.com> + +flashrom -V: http://paste.flashrom.org/view.php?id=370 +lspci: http://paste.flashrom.org/view.php?id=371 +superiotool: http://paste.flashrom.org/view.php?id=372 and + http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html + +Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +------------------------------------------------------------------------ +r1264 \| hailfinger \| 2011-03-05 17:31:57 +0100 (Sat, 05 Mar 2011) \| 9 lines + +I tested a few mainboards and flash chips. +Successfully tested MSI MS-7596 (785GM-E51). +Successfully tested ASRock 890GX Extreme3. +Successfully tested Winbond W25x80. +Mention which GIGABYTE GA-MA78G-DS3H board revision was tested. + +Signed-off-by: Yul Rottmann <yulrottmann@bitel.net> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1263 \| hailfinger \| 2011-03-01 00:58:15 +0100 (Tue, 01 Mar 2011) \| 23 lines + +Update the ITE IT8500 EC support to match the current state of the +flashrom-chromium tree. + +This code has been deployed and tested to work on the Cr-48. +There are a few caveats, though: +- The boot BIOS straps register must be modified to select LPC. This + can be done with the "select_bbs.sh" script (Install iotools at + http://code.google.com/p/iotools/ before using select_bbs). +- It is very important to disable power management daemons before + running flashrom on this EC. I commented out the brute force method + we use in the Chromium OS branch that disables powerd, since IIRC + Carl-Daniel has a better approach in the works. +- Due to dependencies which may be introduced by the OEM/ODM EC + firmware, the code is not guaranteed to work for anything other than + the Cr-48. + +Signed-off-by: David Hendricks <dhendrix@google.com> + +Carl-Daniel comments: +Code is not hooked up yet because probing needs to be sorted out. + +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1262 \| hailfinger \| 2011-02-22 18:16:34 +0100 (Tue, 22 Feb 2011) \| 12 lines + +Add generalized support for ITE IT8500/IT8502 embedded controllers. + +The patch was developed by Google. +It was tested for IT8500E on a Chrome OS platform and may require +modification depending on ODM/OEM customization and EC firmware version. +This patch is not officially supported by ITE Tech Inc. + +Signed-off-by: Donald Huang <donald.huang@ite.com.tw> +Signed-off-by: Yung-chieh Lo <yjlou@google.com> +Signed-off-by: David Hendricks <dhendrix@google.com> +Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> + +------------------------------------------------------------------------ +r1261 \| hailfinger \| 2011-02-15 23:44:27 +0100 (Tue, 15 Feb 2011) \| 14 lines + +Support 64-bit MEM BARs wherever possible. +Add more sanity checks for BARs and abort if resources are unreachable. +Undecoded resources are reported, but flashrom will proceed anyway just +in case the BIOS screwed up the configuration. + +(The empty CardBus handler is intentional, according to the spec no BARs +in PCI config space are used by CardBus.) + +Found while working on a driver for the Angelbird PCIe-based SSD which +has 64-bit capable MEM BARs. + +Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> +Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> + +------------------------------------------------------------------------ r1260 \| hailfinger \| 2011-02-05 13:11:17 +0100 (Sat, 05 Feb 2011) \| 8 lines Add support for AMD Am29LV001BB, Am29LV001BT, Am29LV002BB, Am29LV002BT,
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/Makefile ^
@@ -28,6 +28,8 @@ MANDIR ?= $(PREFIX)/share/man CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . +AR ?= ar +RANLIB ?= ranlib WARNERROR ?= yes @@ -42,8 +44,8 @@ endif ifeq ($(OS_ARCH), Darwin) CPPFLAGS += -I/opt/local/include -I/usr/local/include -# DirectIO framework can be found in the DirectHW library. -LDFLAGS += -framework IOKit -framework DirectIO -L/opt/local/lib -L/usr/local/lib +# DirectHW framework can be found in the DirectHW library. +LDFLAGS += -framework IOKit -framework DirectHW -L/opt/local/lib -L/usr/local/lib endif ifeq ($(OS_ARCH), FreeBSD) CPPFLAGS += -I/usr/local/include @@ -82,6 +84,39 @@ endif endif +ifeq ($(OS_ARCH), libpayload) +CC:=CC=i386-elf-gcc lpgcc +AR:=i386-elf-ar +RANLIB:=i386-elf-ranlib +CPPFLAGS += -DSTANDALONE +ifeq ($(CONFIG_DUMMY), yes) +UNSUPPORTED_FEATURES += CONFIG_DUMMY=yes +else +override CONFIG_DUMMY = no +endif +ifeq ($(CONFIG_BUSPIRATE_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_BUSPIRATE_SPI=yes +else +override CONFIG_BUSPIRATE_SPI = no +endif +ifeq ($(CONFIG_SERPROG), yes) +UNSUPPORTED_FEATURES += CONFIG_SERPROG=yes +else +override CONFIG_SERPROG = no +endif +# Dediprog and FT2232 are not supported with libpayload (missing libusb support) +ifeq ($(CONFIG_DEDIPROG), yes) +UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes +else +override CONFIG_DEDIPROG = no +endif +ifeq ($(CONFIG_FT2232_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes +else +override CONFIG_FT2232_SPI = no +endif +endif + CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o @@ -98,7 +133,7 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := 1260 +SVNVERSION := 1285 RELEASE := 0.9.3 VERSION := $(RELEASE)-r$(SVNVERSION) @@ -184,7 +219,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif @@ -335,11 +370,16 @@ # We could use PULLED_IN_LIBS, but that would be ugly. FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") -OBJS = $(CHIP_OBJS) $(CLI_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +OBJS = $(CLI_OBJS) $(LIBFLASHROM_OBJS) $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(FEATURE_LIBS) $(LIBS) +libflashrom.a: $(LIBFLASHROM_OBJS) + $(AR) rcs $@ $^ + $(RANLIB) $@ + # TAROPTIONS reduces information leakage from the packager's system. # If other tar programs support command line arguments for setting uid/gid of # stored files, they can be handled here as well. @@ -352,7 +392,7 @@ # This includes all frontends and libflashrom. # We don't use EXEC_SUFFIX here because we want to clean everything. clean: - rm -f $(PROGRAM) $(PROGRAM).exe .o .d + rm -f $(PROGRAM) $(PROGRAM).exe libflashrom.a .o .d distclean: clean rm -f .features .libdeps
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/atahpt.c ^
@@ -44,8 +44,7 @@ get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_HPT, PCI_BASE_ADDRESS_4, - ata_hpt); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/board_enable.c ^
@@ -543,7 +543,10 @@ return it8707f_write_enable(0x2e); } -static int pc87360_gpio_set(uint8_t gpio, int raise) +#define PC87360_ID 0xE1 +#define PC87364_ID 0xE4 + +static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; @@ -552,13 +555,13 @@ uint8_t id, val; if (gpio_bank > 4) { - msg_perr("PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC8736x: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); - if (id != 0xE1) { - msg_perr("PC87360: unexpected ID %02x\n", id); + if (id != chipid) { + msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); return -1; } @@ -866,6 +869,7 @@ case 0x00E0: /* CK8 / break; case 0x0260: / MCP51 / + case 0x0261: / MCP51 / case 0x0364: / MCP55 / / find SMBus controller on this southbridge / / The infamous Tyan S2915-E has two south bridges; they are @@ -1026,7 +1030,8 @@ /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 / static int nvidia_mcp_gpio3b_raise(void) { @@ -1453,6 +1458,7 @@ - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R + * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5 @@ -1483,9 +1489,22 @@ int ret; ret = intel_ich_gpio_set(25, 1); /* Master write enable ? / if (!ret) - ret = pc87360_gpio_set(0x09, 1); / #WP ? / + ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); / #WP ? / + if (!ret) + ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); / #TBL / + return ret; +} + +/ + * Suited for: + * - HP e-Vectra P2706T: 810E + ICH + PC87364 + / +static int board_hp_p2706t(void) +{ + int ret; + ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1); if (!ret) - ret = pc87360_gpio_set(0x27, 1); / #TBL */ + ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1); return ret; } @@ -1918,6 +1937,7 @@ {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, @@ -1938,14 +1958,16 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, + {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise}, - {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/cbtable.c ^
@@ -237,7 +237,7 @@ } if (!lb_table) { - msg_pinfo("No coreboot table found.\n"); + msg_pdbg("No coreboot table found.\n"); return -1; }
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/chipdrivers.h ^
@@ -110,6 +110,7 @@ int unlock_sst_fwhub(struct flashchip flash); / w39.c / +int printlock_w39l040(struct flashchip flash); int printlock_w39v040a(struct flashchip flash); int printlock_w39v040b(struct flashchip flash); int printlock_w39v040c(struct flashchip *flash);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/chipset_enable.c ^
@@ -1011,7 +1011,7 @@ {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600}, {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, @@ -1188,7 +1188,7 @@ "\"%s %s\"\n" "ignoring, please report lspci and board URL " "to flashrom@flashrom.org\n" - "with 2CHIPSET: your board name in the " + "with \'CHIPSET: your board name\' in the " "subject line.\n", chipset_enables[i].vendor_name, chipset_enables[i].device_name);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/drkaiser.c ^
@@ -43,8 +43,7 @@ get_io_perms(); - addr = pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2, - drkaiser_pcidev); + addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); /* Write magic register to enable flash write. */ rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR,
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/flashchips.c ^
@@ -3829,7 +3829,7 @@ .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4933,7 +4933,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP \| FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) / .block_erasers = @@ -5567,7 +5567,7 @@ .total_size = 64, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, / 150 ns / .block_erasers = @@ -5804,7 +5804,7 @@ .total_size = 256, .page_size = 16 1024, .feature_bits = FEATURE_REGISTERMAP \| FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns / .block_erasers = @@ -5869,7 +5869,7 @@ .total_size = 512, .page_size = 64 1024, .feature_bits = FEATURE_REGISTERMAP \| FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns / .block_erasers = @@ -6144,7 +6144,7 @@ .total_size = 1024, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_FIXME, .block_erasers = @@ -6516,6 +6516,35 @@ { .vendor = "ST", + .name = "M25PX16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25PX16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 1024, 512 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25PX32", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, @@ -7597,7 +7626,7 @@ .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7820,6 +7849,36 @@ { .vendor = "Winbond", + .name = "W39L040", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39L040, + .total_size = 512, + .page_size = 64 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_OK_PR, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39l040, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "Winbond", .name = "W39V040A", .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, @@ -7939,7 +7998,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP \| FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers =
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/flashchips.h ^
@@ -533,6 +533,7 @@ #define ST_M25P32 0x2016 #define ST_M25P64 0x2017 #define ST_M25P128 0x2018 +#define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 #define ST_M25PX64 0x7117 #define ST_M25PE10 0x8011
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/flashrom.c ^
@@ -61,7 +61,6 @@ #endif #if CONFIG_NICREALTEK == 1 PROGRAMMER_NICREALTEK - PROGRAMMER_NICREALTEK2 #endif #if CONFIG_NICNATSEMI == 1 PROGRAMMER_NICNATSEMI @@ -182,7 +181,9 @@ #if CONFIG_NICREALTEK == 1 { + /* This programmer works for Realtek RTL8139 and SMC 1211. */ .name = "nicrealtek", + //.name = "nicsmc1211", .init = nicrealtek_init, .shutdown = nicrealtek_shutdown, .map_flash_region = fallback_map, @@ -197,22 +198,6 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, - { - .name = "nicsmc1211", - .init = nicsmc1211_init, - .shutdown = nicrealtek_shutdown, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicrealtek_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicrealtek_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, - .delay = internal_delay, - }, #endif #if CONFIG_NICNATSEMI == 1 @@ -1201,11 +1186,12 @@ if (!flash \|\| !flash->name) return NULL; - if (programmer_table[programmer].map_flash_region == physmap) { +#if CONFIG_INTERNAL == 1 + if (programmer_table[programmer].map_flash_region == physmap) snprintf(location, sizeof(location), "at physical address 0x%lx", base); - } else { + else +#endif snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); - } msg_cinfo("%s chip \"%s %s\" (%d KB, %s) %s.\n", force ? "Assuming" : "Found",
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/gfxnvidia.c ^
@@ -66,8 +66,7 @@ get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_NVIDIA, PCI_BASE_ADDRESS_0, - gfx_nvidia); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/hwaccess.h ^
@@ -194,7 +194,7 @@ #else #if defined(__DARWIN__) /* Header is part of the DirectHW library. */ - #include <DirectIO/darwinio.h> + #include <DirectHW/DirectHW.h> #define off64_t off_t #define lseek64 lseek #endif
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/ichspi.c ^
@@ -51,6 +51,7 @@ #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 +#define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits / #define SSFC_SCGO 0x00000200 @@ -63,6 +64,7 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_RESERVED_MASK 0xf8008100 #define ICH9_REG_PREOP 0x94 / 16 Bits / #define ICH9_REG_OPTYPE 0x96 / 16 Bits / @@ -76,9 +78,11 @@ // ICH7 registers #define ICH7_REG_SPIS 0x00 / 16 Bits / -#define SPIS_SCIP 0x00000001 -#define SPIS_CDS 0x00000004 -#define SPIS_FCERR 0x00000008 +#define SPIS_SCIP 0x0001 +#define SPIS_GRANT 0x0002 +#define SPIS_CDS 0x0004 +#define SPIS_FCERR 0x0008 +#define SPIS_RESERVED_MASK 0x7ff0 / VIA SPI is compatible with ICH7, but maxdata to transfer is 16 bytes. @@ -146,6 +150,11 @@ return mmio_readw(ich_spibar + X); } +static uint16_t REGREAD8(int X) +{ + return mmio_readb(ich_spibar + X); +} + #define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) #define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) #define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) @@ -497,6 +506,15 @@ write_cmd = 1; } + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. / + while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("Error: SCIP never cleared!\n"); + return 1; + } + / Programm Offset in Flash into FADDR / REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); / SPI addresses are 24 BIT only / @@ -523,7 +541,9 @@ } / Assemble SPIS / - temp16 = 0; + temp16 = REGREAD16(ICH7_REG_SPIS); + / keep reserved bits / + temp16 &= SPIS_RESERVED_MASK; / clear error status registers / temp16 \|= (SPIS_CDS + SPIS_FCERR); REGWRITE16(ICH7_REG_SPIS, temp16); @@ -570,18 +590,26 @@ / write it / REGWRITE16(ICH7_REG_SPIC, temp16); - / wait for cycle complete / - timeout = 100 1000 * 60; // 60s is a looong timeout. - while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. / + timeout = 100 60; /* 60 ms are 9.6 million cycles at 16 MHz. / + while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS \| SPIS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { - msg_perr("timeout\n"); + msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", + REGREAD16(ICH7_REG_SPIS)); + return 1; } / FIXME: make sure we do not needlessly cause transaction errors. / - if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + temp16 = REGREAD16(ICH7_REG_SPIS); + if (temp16 & SPIS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + / keep reserved bits / + temp16 &= SPIS_RESERVED_MASK; + REGWRITE16(ICH7_REG_SPIS, temp16 \| SPIS_FCERR); return 1; } @@ -616,6 +644,15 @@ write_cmd = 1; } + timeout = 100 60; /* 60 ms are 9.6 million cycles at 16 MHz. / + while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("Error: SCIP never cleared!\n"); + return 1; + } + / Programm Offset in Flash into FADDR / REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); / SPI addresses are 24 BIT only / @@ -641,12 +678,13 @@ } / Assemble SSFS + SSFC / - / keep reserved bits (23-19,7,0) / temp32 = REGREAD32(ICH9_REG_SSFS); - temp32 &= 0xF8008100; - + / keep reserved bits / + temp32 &= SSFS_RESERVED_MASK \| SSFC_RESERVED_MASK; / clear error status registers / temp32 \|= (SSFS_CDS + SSFS_FCERR); + REGWRITE32(ICH9_REG_SSFS, temp32); + / Use 20 MHz / temp32 \|= SSFC_SCF_20MHZ; @@ -691,18 +729,27 @@ / write it / REGWRITE32(ICH9_REG_SSFS, temp32); - /wait for cycle complete / - timeout = 100 1000 * 60; // 60s is a looong timeout. - while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. / + timeout = 100 60; /* 60 ms are 9.6 million cycles at 16 MHz. / + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS \| SSFS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { - msg_perr("timeout\n"); + msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n", + REGREAD32(ICH9_REG_SSFS)); + return 1; } / FIXME make sure we do not needlessly cause transaction errors. / - if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + temp32 = REGREAD32(ICH9_REG_SSFS); + if (temp32 & SSFS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + / keep reserved bits / + temp32 &= SSFS_RESERVED_MASK \| SSFC_RESERVED_MASK; + / Clear the transaction error. */ + REGWRITE32(ICH9_REG_SSFS, temp32 \| SSFS_FCERR); return 1; } @@ -1042,7 +1089,6 @@ msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(ich_spibar + offs), i); } - msg_pdbg("\n"); if (mmio_readw(ich_spibar) & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; @@ -1082,8 +1128,20 @@ mmio_readl(ich_spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(ich_spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(ich_spibar + 0x90)); + + tmp = mmio_readl(ich_spibar + 0x90); + msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); + msg_pdbg("AEL %i, ", (tmp >> 4) & 1); + msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); + msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); + msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + if (tmp & (1 << 3)) { + msg_pdbg("Clearing SSFS.FCERR\n"); + mmio_writeb(1 << 3, ich_spibar + 0x90); + } + tmp >>= 8; + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
[-] [+]	Added	flashrom-0.9.3_r1285.tar.bz2/it85spi.c ^
@@ -0,0 +1,420 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl> + * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2010 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + / + +/ + * Contains the ITE IT85* SPI specific routines + / + +#if defined(__i386__) \|\| defined(__x86_64__) + +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" + +#define MAX_TIMEOUT 100000 +#define MAX_TRY 5 + +/ Constants for I/O ports / +#define ITE_SUPERIO_PORT1 0x2e +#define ITE_SUPERIO_PORT2 0x4e + +/ Legacy I/O / +#define LEGACY_KBC_PORT_DATA 0x60 +#define LEGACY_KBC_PORT_CMD 0x64 + +/ Constants for Logical Device registers / +#define LDNSEL 0x07 +#define CHIP_ID_BYTE1_REG 0x20 +#define CHIP_ID_BYTE2_REG 0x21 +#define CHIP_CHIP_VER_REG 0x22 + +/ These are standard Super I/O 16-bit base address registers / +#define SHM_IO_BAR0 0x60 / big-endian, this is high bits / +#define SHM_IO_BAR1 0x61 + +/ The 8042 keyboard controller uses an input buffer and an output buffer to + * communicate with the host CPU. Both buffers are 1-byte depth. That means + * IBF is set to 1 when the host CPU sends a command to the input buffer + * of the EC. IBF is cleared to 0 once the command is read by the EC. + / +#define KB_IBF (1 << 1) / Input Buffer Full / +#define KB_OBF (1 << 0) / Output Buffer Full / + +/ IT8502 supports two access modes: + * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode) + * LPC_IO: through I/O port (so called indirect memory) + / +#undef LPC_MEMORY +#define LPC_IO + +#ifdef LPC_IO +/ macro to fill in indirect-access registers. / +#define INDIRECT_A0(base, value) OUTB(value, (base) + 0) / little-endian / +#define INDIRECT_A1(base, value) OUTB(value, (base) + 1) +#define INDIRECT_A2(base, value) OUTB(value, (base) + 2) +#define INDIRECT_A3(base, value) OUTB(value, (base) + 3) +#define INDIRECT_READ(base) INB((base) + 4) +#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4) +#endif / LPC_IO / + +#ifdef LPC_IO +unsigned int shm_io_base; +#endif +unsigned char ce_high, ce_low; +static int it85xx_scratch_rom_reenter = 0; + +uint16_t probe_id_ite85(uint16_t port) +{ + uint16_t id; + + id = sio_read(port, CHIP_ID_BYTE1_REG) << 8 \| + sio_read(port, CHIP_ID_BYTE2_REG); + + return id; +} + +struct superio probe_superio_ite85xx(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t i = ite_ports; + + ret.vendor = SUPERIO_VENDOR_ITE; + for (; i; i++) { + ret.port = i; + ret.model = probe_id_ite85(ret.port); + switch (ret.model >> 8) { + case 0x85: + msg_pdbg("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x," + "Rev:0x%02x) on sio_port:0x%x.\n", + ret.model >> 8, ret.model & 0xff, + sio_read(ret.port, CHIP_CHIP_VER_REG), + ret.port); + return ret; + } + } + + /* No good ID found. / + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +/ This function will poll the keyboard status register until either + * an expected value shows up, or + * timeout reaches. + * + * Returns: 0 -- the expected value has shown. + * 1 -- timeout reached. + / +static int wait_for( + const unsigned int mask, + const unsigned int expected_value, + const int timeout, / in usec / + const char error_message, + const char* function_name, + const int lineno +) { + int time_passed; + + for (time_passed = 0;; ++time_passed) { + if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value) + return 0; + if (time_passed >= timeout) + break; + programmer_delay(1); + } + if (error_message) + msg_perr("%s():%d %s", function_name, lineno, error_message); + return 1; +} + +/* IT8502 employs a scratch ram when flash is being updated. Call the following + * two functions before/after flash erase/program. / +void it85xx_enter_scratch_rom() +{ + int ret; + int tries; + + msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__); + if (it85xx_scratch_rom_reenter > 0) return; + +#if 0 + / FIXME: this a workaround for the bug that SMBus signal would + * interfere the EC firmware update. Should be removed if + * we find out the root cause. / + ret = system("stop powerd >&2"); + if (ret) { + msg_perr("Cannot stop powerd.\n"); + } +#endif + + for (tries = 0; tries < MAX_TRY; ++tries) { + / Wait until IBF (input buffer) is not full. / + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + " timeout at waiting for IBF==0.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Copy EC firmware to SRAM. / + OUTB(0xb4, LEGACY_KBC_PORT_CMD); + + / Confirm EC has taken away the command. / + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + " timeout at taking command.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Waiting for OBF (output buffer) has data. + * Note sometimes the replied command might be stolen by kernel + * ISR so that it is okay as long as the command is 0xFA. / + if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0)) + msg_pdbg("%s():%d timeout at waiting for OBF.\n", + __FUNCTION__, __LINE__); + if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) { + break; + } else { + msg_perr("%s():%d * not run on SRAM ret=%d\n", + __FUNCTION__, __LINE__, ret); + continue; + } + } + + if (tries < MAX_TRY) { + /* EC already runs on SRAM / + it85xx_scratch_rom_reenter++; + msg_pdbg("%s():%d SUCCESS.\n", __FUNCTION__, __LINE__); + } else { + msg_perr("%s():%d * Max try reached.\n", + __FUNCTION__, __LINE__); + } +} + +void it85xx_exit_scratch_rom() +{ +#if 0 + int ret; +#endif + int tries; + + msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__); + if (it85xx_scratch_rom_reenter <= 0) return; + + for (tries = 0; tries < MAX_TRY; ++tries) { + /* Wait until IBF (input buffer) is not full. / + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + " timeout at waiting for IBF==0.\n", + __FUNCTION__, __LINE__)) + continue; + + /* Exit SRAM. Run on flash. / + OUTB(0xFE, LEGACY_KBC_PORT_CMD); + + / Confirm EC has taken away the command. / + if (wait_for(KB_IBF, 0, MAX_TIMEOUT, + " timeout at taking command.\n", + __FUNCTION__, __LINE__)) { + /* We cannot ensure if EC has exited update mode. + * If EC is in normal mode already, a further 0xFE + * command will reboot system. So, exit loop here. / + tries = MAX_TRY; + break; + } + + break; + } + + if (tries < MAX_TRY) { + it85xx_scratch_rom_reenter = 0; + msg_pdbg("%s():%d SUCCESS.\n", __FUNCTION__, __LINE__); + } else { + msg_perr("%s():%d * Max try reached.\n", + __FUNCTION__, __LINE__); + } + +#if 0 + /* FIXME: this a workaround for the bug that SMBus signal would + * interfere the EC firmware update. Should be removed if + * we find out the root cause. / + ret = system("start powerd >&2"); + if (ret) { + msg_perr("Cannot start powerd again.\n"); + } +#endif +} + +int it85xx_spi_common_init(void) +{ + chipaddr base; + + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, + superio.vendor); + if (superio.vendor != SUPERIO_VENDOR_ITE) + return 1; + +#ifdef LPC_IO + / Get LPCPNP of SHM. That's big-endian / + sio_write(superio.port, LDNSEL, 0x0F); / Set LDN to SHM (0x0F) / + shm_io_base = (sio_read(superio.port, SHM_IO_BAR0) << 8) + + sio_read(superio.port, SHM_IO_BAR1); + msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, + shm_io_base); + + / These pointers are not used directly. They will be send to EC's + * register for indirect access. / + base = 0xFFFFF000; + ce_high = ((unsigned char)base) + 0xE00; /* 0xFFFFFE00 / + ce_low = ((unsigned char)base) + 0xD00; /* 0xFFFFFD00 / + + / pre-set indirect-access registers since in most of cases they are + * 0xFFFFxx00. / + INDIRECT_A0(shm_io_base, base & 0xFF); + INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF); + INDIRECT_A3(shm_io_base, (base >> 24)); +#endif +#ifdef LPC_MEMORY + base = (chipaddr)programmer_map_flash_region("it85 communication", + 0xFFFFF000, 0x1000); + msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, + (unsigned int)base); + ce_high = (unsigned char)(base + 0xE00); /* 0xFFFFFE00 / + ce_low = (unsigned char)(base + 0xD00); /* 0xFFFFFD00 / +#endif + + / Set this as spi controller. / + spi_controller = SPI_CONTROLLER_IT85XX; + + return 0; +} + +/ Called by programmer_entry .init / +int it85xx_spi_init(void) +{ + int ret; + + get_io_perms(); + / Probe for the Super I/O chip and fill global struct superio. / + probe_superio(); + ret = it85xx_spi_common_init(); + if (!ret) { + buses_supported = CHIP_BUSTYPE_SPI; + } else { + buses_supported = CHIP_BUSTYPE_NONE; + } + return ret; +} + +/ Called by internal_init() / +int it85xx_probe_spi_flash(void) +{ + int ret; + + if (!(buses_supported & CHIP_BUSTYPE_FWH)) { + msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); + return 1; + } + ret = it85xx_spi_common_init(); + msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); + if (!ret) { + msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, + buses_supported); + if (buses_supported & CHIP_BUSTYPE_FWH) + msg_pdbg("Overriding chipset SPI with IT85 FWH\|SPI.\n"); + buses_supported \|= CHIP_BUSTYPE_FWH \| CHIP_BUSTYPE_SPI; + } + return ret; +} + +int it85xx_shutdown(void) +{ + msg_pdbg("%s():%d\n", __func__, __LINE__); + it85xx_exit_scratch_rom(); + return 0; +} + +/ According to ITE 8502 document, the procedure to follow mode is following: + * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) + * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI + * with data) + * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get + * data from MISO) + / +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char writearr, unsigned char readarr) +{ + int i; + + it85xx_enter_scratch_rom(); + / exit scratch rom ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt EC. / + +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); / Write anything to this address./ + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); +#endif +#ifdef LPC_MEMORY + mmio_writeb(0, ce_high); +#endif + for (i = 0; i < writecnt; ++i) { +#ifdef LPC_IO + INDIRECT_WRITE(shm_io_base, writearr[i]); +#endif +#ifdef LPC_MEMORY + mmio_writeb(writearr[i], ce_low); +#endif + } + for (i = 0; i < readcnt; ++i) { +#ifdef LPC_IO + readarr[i] = INDIRECT_READ(shm_io_base); +#endif +#ifdef LPC_MEMORY + readarr[i] = mmio_readb(ce_low); +#endif + } +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); / Write anything to this address./ +#endif +#ifdef LPC_MEMORY + mmio_writeb(0, ce_high); +#endif + + return 0; +} + +int it85_spi_read(struct flashchip flash, uint8_t * buf, int start, int len) +{ + return spi_read_chunked(flash, buf, start, len, 64); +} + +int it85_spi_write_256(struct flashchip flash, uint8_t buf, int start, int len) +{ + return spi_write_chunked(flash, buf, start, len, 64); +} + +#endif
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/nic3com.c ^
@@ -59,8 +59,7 @@ { get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_3COM, PCI_BASE_ADDRESS_0, - nics_3com); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); id = pcidev_dev->device_id;
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/nicintel_spi.c ^
@@ -144,8 +144,7 @@ get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_INTEL, PCI_BASE_ADDRESS_0, - nics_intel_spi); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/nicnatsemi.c ^
@@ -39,8 +39,7 @@ { get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_NATSEMI, PCI_BASE_ADDRESS_0, - nics_natsemi); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); buses_supported = CHIP_BUSTYPE_PARALLEL;
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/nicrealtek.c ^
@@ -32,10 +32,6 @@ const struct pcidev_status nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, - {}, -}; - -const struct pcidev_status nics_realteksmc1211[] = { {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */ {}, }; @@ -44,20 +40,7 @@ { get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0, - nics_realtek); - - buses_supported = CHIP_BUSTYPE_PARALLEL; - - return 0; -} - -int nicsmc1211_init(void) -{ - get_io_perms(); - - io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0, - nics_realteksmc1211); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); buses_supported = CHIP_BUSTYPE_PARALLEL;
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/ogp_spi.c ^
@@ -120,8 +120,7 @@ get_io_perms(); - io_base_addr = pcidev_init(PCI_VENDOR_ID_OGP, PCI_BASE_ADDRESS_0, - ogp_spi); + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); ogp_spibar = physmap("OGP registers", io_base_addr, 4096);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/pcidev.c ^
@@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,43 +28,151 @@ struct pci_access pacc; struct pci_dev pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev dev, uint32_t bar, +enum pci_bartype { + TYPE_MEMBAR, + TYPE_IOBAR, + TYPE_ROMBAR, + TYPE_UNKNOWN +}; + +uintptr_t pcidev_validate(struct pci_dev dev, int bar, const struct pcidev_status devs) { int i; - / FIXME: 64 bit memory BARs need a 64 bit addr. / - uint32_t addr; + uint64_t addr; + uint32_t upperaddr; + uint8_t headertype; + uint16_t supported_cycles; + enum pci_bartype bartype = TYPE_UNKNOWN; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); + + headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; + msg_pspew("PCI header type 0x%02x\n", headertype); + / * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. / addr = pci_read_long(dev, bar); - - msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, - dev->vendor_id, dev->device_id, dev->bus, dev->dev, - dev->func); - msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); - if (addr & 0x1) { - / Mask off IO space indicator and reserved bit. / - msg_pdbg("\n"); - addr &= ~0x3; - } else { + + / Sanity checks. / + switch (headertype) { + case PCI_HEADER_TYPE_NORMAL: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_BRIDGE: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS1: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_CARDBUS: + break; + default: + msg_perr("Unknown PCI header type 0x%02x, BAR type " + "cannot be determined reliably.\n", headertype); + break; + } + + supported_cycles = pci_read_word(dev, PCI_COMMAND); + + msg_pdbg("Requested BAR is "); + switch (bartype) { + case TYPE_MEMBAR: + msg_pdbg("MEM"); + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + / TODO: Abort here? / + } msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); - / Mask off Mem space indicator, 32/64bit type indicator - * and Prefetchable indicator. - / - addr &= ~0xf; + if ((addr & 0x6) == 0x4) { + / The spec says that a 64-bit register consumes + * two subsequent dword locations. + / + upperaddr = pci_read_long(dev, bar + 4); + if (upperaddr != 0x00000000) { + / Fun! A real 64-bit resource. / + if (sizeof(uintptr_t) != sizeof(uint64_t)) { + msg_perr("BAR unreachable!"); + / TODO: Really abort here? If + * multiple PCI devices match, + * we might never tell the user + * about the other devices. + / + return 0; + } + addr \|= (uint64_t)upperaddr << 32; + } + } + addr &= PCI_BASE_ADDRESS_MEM_MASK; + break; + case TYPE_IOBAR: + msg_pdbg("I/O\n"); +#if __FLASHROM_HAVE_OUTB__ + if (!(supported_cycles & PCI_COMMAND_IO)) { + msg_perr("I/O BAR access requested, but device " + "has I/O space accesses disabled.\n"); + / TODO: Abort here? / + } +#else + msg_perr("I/O BAR access requested, but flashrom does " + "not support I/O BAR access on this platform " + "(yet).\n"); +#endif + addr &= PCI_BASE_ADDRESS_IO_MASK; + break; + case TYPE_ROMBAR: + msg_pdbg("ROM\n"); + / Not sure if this check is needed. / + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + / TODO: Abort here? / + } + addr &= PCI_ROM_ADDRESS_MASK; + break; + case TYPE_UNKNOWN: + msg_perr("BAR type unknown, please report a bug at " + "flashrom@flashrom.org\n"); } - + if (devs[i].status == NT) { msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" @@ -73,29 +182,27 @@ "your help!\n===\n"); } - return addr; + return (uintptr_t)addr; } return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, - const struct pcidev_status devs) +uintptr_t pcidev_init(int bar, const struct pcidev_status devs) { struct pci_dev dev; struct pci_filter filter; char pcidev_bdf; char msg = NULL; int found = 0; - uint32_t addr = 0, curaddr = 0; + uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure / pci_init(pacc); / Initialize the PCI library / pci_scan_bus(pacc); / We want to get the list of devices / pci_filter_init(pacc, &filter); - / Filter by vendor and also bb:dd.f (if supplied by the user). / - filter.vendor = vendor_id; + / Filter by bb:dd.f (if supplied by the user). / pcidev_bdf = extract_programmer_param("pci"); if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { @@ -107,6 +214,9 @@ for (dev = pacc->devices; dev; dev = dev->next) { if (pci_filter_match(&filter, dev)) { + / FIXME: We should count all matching devices, not + * just those with a valid BAR. + */ if ((addr = pcidev_validate(dev, bar, devs)) != 0) { curaddr = addr; pcidev_dev = dev;
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/physmap.c ^
@@ -134,7 +134,7 @@ } #elif defined(__DARWIN__) -#define MEM_DEV "DirectIO" +#define MEM_DEV "DirectHW" static void *sys_physmap(unsigned long phys_addr, size_t len) { @@ -492,6 +492,7 @@ int libpayload_wrmsr(int addr, msr_t msr) { _wrmsr(addr, msr.lo \| ((unsigned long long)msr.hi << 32)); + return 0; } #else msr_t rdmsr(int addr)
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/print.c ^
@@ -249,9 +249,6 @@ printf("\nSupported devices for the %s programmer:\n", programmer_table[PROGRAMMER_NICREALTEK].name); print_supported_pcidevs(nics_realtek); - printf("\nSupported devices for the %s programmer:\n", - programmer_table[PROGRAMMER_NICREALTEK2].name); - print_supported_pcidevs(nics_realteksmc1211); #endif #if CONFIG_NICNATSEMI == 1 printf("\nSupported devices for the %s programmer:\n", @@ -358,6 +355,7 @@ B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL), B("ASI", "MB-5BLMP", 1, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."), B("ASRock", "775i65G", 1, "http://www.asrock.com/mb/overview.asp?Model=775i65G", NULL), + B("ASRock", "890GX Extreme3", 1, "http://www.asrock.com/mb/overview.asp?Model=890GX%20Extreme3", NULL), B("ASRock", "939A785GMH/128M", 1, "http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939", NULL), B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2%%2b", NULL), @@ -462,6 +460,7 @@ B("EPoX", "EP-8NPA7I", 1, "http://epox.com/product.asp?ID=EP-8NPA7I", NULL), B("EPoX", "EP-8RDA3+", 1, "http://www.epox.com/product.asp?ID=EP-8RDA3plus", NULL), B("EPoX", "EP-BX3", 1, "http://www.epox.com/product.asp?ID=EP-BX3", NULL), + B("EVGA", "132-CK-NF78", 1, "http://http://www.evga.com/articles/385.asp", NULL), B("FIC", "VA-502", 0, "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/", "No public report found. Owned by Uwe Hermann <uwe@hermann-uwe.de>. Seems the PCI subsystem IDs are identical with the Tekram P6Pro-A5. May work now."), B("Foxconn", "A6VMX", 1, "http://www.foxconnchannel.com/product/motherboards/detail_overview.aspx?id=en-us0000346", NULL), B("Fujitsu-Siemens", "ESPRIMO P5915", 1, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/professionalpc/ESPRIMO/P/EsprimoP5915-6.htm", "Mainboard model is D2312-A2."), @@ -481,17 +480,20 @@ B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), B("GIGABYTE", "GA-MA69VM-S2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2500", NULL), B("GIGABYTE", "GA-MA74GM-S2H (rev. 3.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3152", NULL), B("GIGABYTE", "GA-MA770T-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3096", NULL), - B("GIGABYTE", "GA-MA78G-DS3H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), /* TODO: Rev 1.x or 2.x? / + B("GIGABYTE", "GA-MA780G-UD3H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3004", NULL), + B("GIGABYTE", "GA-MA78G-DS3H (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), B("GIGABYTE", "GA-MA78GM-S2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2758", NULL), / TODO: Rev. 1.0, 1.1, or 2.x? */ B("GIGABYTE", "GA-MA78GPM-DS2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), + B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&prodSeriesId=77515&prodTypeId=12454", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-3328421-3955644.html", NULL), B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL), @@ -541,6 +543,7 @@ B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1261", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL), B("MSI", "MS-7376 (K9A2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL), + B("MSI", "MS-7596 (785GM-E51)", 1, "http://eu.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1866", NULL), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", 1, NULL, NULL),
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/print_wiki.c ^
@@ -246,6 +246,8 @@ printf("\n\|}\n\n\|}\n"); } +/* Not needed for CONFIG_INTERNAL, but for all other PCI-based programmers. / +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 static void print_supported_pcidevs_wiki(const struct pcidev_status devs) { int i = 0; @@ -262,6 +264,7 @@ (devs[i].status == NT) ? "?3" : "OK"); } } +#endif void print_supported_wiki(void) { @@ -279,7 +282,6 @@ #endif #if CONFIG_NICREALTEK == 1 print_supported_pcidevs_wiki(nics_realtek); - print_supported_pcidevs_wiki(nics_realteksmc1211); #endif #if CONFIG_NICNATSEMI == 1 print_supported_pcidevs_wiki(nics_natsemi);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/programmer.h ^
@@ -36,7 +36,6 @@ #endif #if CONFIG_NICREALTEK == 1 PROGRAMMER_NICREALTEK, - PROGRAMMER_NICREALTEK2, #endif #if CONFIG_NICNATSEMI == 1 PROGRAMMER_NICNATSEMI, @@ -219,8 +218,8 @@ const char vendor_name; const char device_name; }; -uint32_t pcidev_validate(struct pci_dev dev, uint32_t bar, const struct pcidev_status devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status devs); +uintptr_t pcidev_validate(struct pci_dev dev, int bar, const struct pcidev_status devs); +uintptr_t pcidev_init(int bar, const struct pcidev_status devs); /* rpci_write_* are reversible writes. The original PCI config space register * contents will be restored on shutdown. / @@ -230,7 +229,7 @@ #endif / print.c / -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 void print_supported_pcidevs(const struct pcidev_status devs); #endif @@ -384,12 +383,10 @@ /* nicrealtek.c / #if CONFIG_NICREALTEK == 1 int nicrealtek_init(void); -int nicsmc1211_init(void); int nicrealtek_shutdown(void); void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicrealtek_chip_readb(const chipaddr addr); extern const struct pcidev_status nics_realtek[]; -extern const struct pcidev_status nics_realteksmc1211[]; #endif / nicnatsemi.c / @@ -523,6 +520,7 @@ #if defined(__i386__) \|\| defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, @@ -583,6 +581,16 @@ int ich_spi_send_multicommand(struct spi_command cmds); #endif +/* it85spi.c / +struct superio probe_superio_ite85xx(void); +int it85xx_spi_init(void); +int it85xx_shutdown(void); +int it85xx_probe_spi_flash(void); +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char writearr, unsigned char readarr); +int it85_spi_read(struct flashchip flash, uint8_t * buf, int start, int len); +int it85_spi_write_256(struct flashchip flash, uint8_t buf, int start, int len); + /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port);
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/satamv.c ^
@@ -67,7 +67,7 @@ /* No need to check for errors, pcidev_init() will not return in case * of errors. */ - addr = pcidev_init(0x11ab, PCI_BASE_ADDRESS_0, satas_mv); + addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR)
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/satasii.c ^
@@ -47,7 +47,7 @@ get_io_perms(); - pcidev_init(PCI_VENDOR_ID_SII, PCI_BASE_ADDRESS_0, satas_sii); + pcidev_init(PCI_BASE_ADDRESS_0, satas_sii); id = pcidev_dev->device_id;
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/spi.c ^
@@ -22,6 +22,7 @@ * Contains the generic SPI framework / +#include <strings.h> #include <string.h> #include "flash.h" #include "flashchips.h" @@ -55,6 +56,13 @@ .write_256 = ich_spi_write_256, }, + { / SPI_CONTROLLER_IT85XX / + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it85_spi_read, + .write_256 = it85_spi_write_256, + }, + { / SPI_CONTROLLER_IT87XX */ .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand,
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/udelay.c ^
@@ -182,6 +182,7 @@ } #else +#include <libpayload.h> void myusec_calibrate_delay(void) {
[-] [+]	Changed	flashrom-0.9.3_r1285.tar.bz2/w39.c ^
@@ -161,6 +161,22 @@ return 0; } +int printlock_w39l040(struct flashchip * flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_bootblock_64k16k(lock); + + lock = w39_idmode_readb(flash, 0x7fff2); + msg_cdbg("Top boot block:\n"); + ret \|= printlock_w39_bootblock_64k16k(lock); + + return ret; +} + int printlock_w39v040a(struct flashchip *flash) { uint8_t lock;